Patents by Inventor I-I Chen
I-I Chen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 7482265Abstract: A method of manufacturing a semiconductor device having a low-k dielectric layer is provided. An embodiment comprises forming a dielectric layer on a substrate, wherein the layer comprises a pore generating material dispersed in an uncured matrix. A second step comprises forming pores in the uncured matrix by irradiating the layer with radiation having a first wavelength. After pore forming, a third step comprises cross-linking the dielectric by irradiating it at a second wavelength, the second being less than the first. In an embodiment, the irradiating wavelengths comprise ultra-violet radiation. Embodiments may further include repairing processing damage wherein the damage includes dangling bonds or silanol formation. The repairing includes annealing in a carbon-containing ambient such as C2H4, C3H6, or hexamethyldisilazane (HMDS).Type: GrantFiled: January 10, 2006Date of Patent: January 27, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-I Chen, Tien-I Bao, Shwang-Ming Cheug, Chen-Hua Yu
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Patent number: 7465676Abstract: A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.Type: GrantFiled: April 24, 2006Date of Patent: December 16, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Fang Wen Tsai, I-I Chen, Zhen-Cheng Wu, Chih-Lung Lin, Tien-I Bao, Shwang-Ming Jeng, Chen-Hua Yu
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Publication number: 20080188074Abstract: A method for forming a cap layer for an interconnect structure is provided. The method includes providing a substrate; depositing a low-k dielectric layer comprising a first porogen over the substrate; depositing a low-k cap layer comprising a second porogen on the low-k dielectric layer; and curing the low-k dielectric layer and the low-k cap layer simultaneously to remove the first and the second porogens, so that a first porosity in the low-k dielectric layer and a second porosity in the low-k cap layer are created. The second porosity is preferably less than the first porosity. Preferably, the low-k dielectric layer and the low-k cap layer comprise a common set of precursors and porogens, and are in-situ performed.Type: ApplicationFiled: March 27, 2007Publication date: August 7, 2008Inventors: I-I Chen, Fang Wen Tsai, Zhen-Cheng Wu, Tien-I Bao, Shwang-Ming Jeng, Chen-Hua Yu
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Publication number: 20080116578Abstract: An integrated circuit includes an etch stop layer over a substrate; a UV blocker layer on the etch stop layer, wherein the UV blocker layer has a high extinction coefficient; and a low-k dielectric layer on the UV blocker layer.Type: ApplicationFiled: November 21, 2006Publication date: May 22, 2008Inventors: Kuan-Chen Wang, Zhen-Cheng Wu, Fang Wen Tsai, Yih-Hsing Lo, I-I Chen, Tien-I Bao, Shwang-Ming Jeng
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Publication number: 20070249159Abstract: A semiconductor structure having improved adhesion between a low-k dielectric layer and the underlying layer and a method for forming the same are provided. The semiconductor substrate includes a dielectric layer over a semiconductor substrate, an adhesion layer on the dielectric layer wherein the adhesion layer comprises a transition sub-layer over an initial sub-layer, and wherein the transition sub-layer has a composition that gradually changes from a lower portion to an upper portion. A low-k dielectric layer is formed on the adhesion layer. Damascene openings are formed in the low-k dielectric layer. A top portion of the transition sub-layer has a composition substantially similar to a composition of the low-k dielectric layer. A bottom portion of the transition sub-layer has a composition substantially similar to a composition of the initial sub-layer.Type: ApplicationFiled: April 24, 2006Publication date: October 25, 2007Inventors: Fang Tsai, I-I Chen, Zhen-Cheng Wu, Chih-Lung Lin, Tien-I Bao, Shwang-Ming Jeng, Chen-Hua Yu
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Publication number: 20070161230Abstract: A method of manufacturing a semiconductor device having a low-k dielectric layer is provided. An embodiment comprises forming a dielectric layer on a substrate, wherein the layer comprises a pore generating material dispersed in an uncured matrix. A second step comprises forming pores in the uncured matrix by irradiating the layer with radiation having a first wavelength. After pore forming, a third step comprises cross-linking the dielectric by irradiating it at a second wavelength, the second being less than the first. In an embodiment, the irradiating wavelengths comprise ultra-violet radiation. Embodiments may further include repairing processing damage wherein the damage includes dangling bonds or silanol formation. The repairing includes annealing in a carbon-containing ambient such as C2H4, C3H6, or hexamethyldisilazane (HMDS).Type: ApplicationFiled: January 10, 2006Publication date: July 12, 2007Inventors: I-I Chen, Tien-I Bao, Shwang-Ming Cheng, Chen-Hua Yu
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Patent number: 7094705Abstract: A method for plasma treating an exposed copper surface and dielectric insulating layer in a semiconductor device manufacturing process including providing a semiconductor wafer having a process surface including an exposed copper portion and an exposed dielectric insulating layer portion; plasma treating in a first plasma treatment process, the process surface with a first plasma including ammonia (NH3) and nitrogen (N2) plasma to form a copper nitride layer overlying the exposed copper portion; and, plasma treating in a second plasma treatment process the process surface with a second plasma including oxygen (O2).Type: GrantFiled: January 20, 2004Date of Patent: August 22, 2006Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Keng-Chu Lin, Hui-Lin Chang, I-I Chen, Yung-Chen Lu, Syun-Ming Jeng
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Publication number: 20050158999Abstract: A method for plasma treating an exposed copper surface and dielectric insulating layer in a semiconductor device manufacturing process including providing a semiconductor wafer having a process surface including an exposed copper portion and an exposed dielectric insulating layer portion; plasma treating in a first plasma treatment process, the process surface with a first plasma including ammonia (NH3) and nitrogen (N2) plasma to form a copper nitride layer overlying the exposed copper portion; and, plasma treating in a second plasma treatment process the process surface with a second plasma including oxygen (O2).Type: ApplicationFiled: January 20, 2004Publication date: July 21, 2005Inventors: Keng-Chu Lin, Hui-Lin Chang, I-I Chen, Yung-Chen Lu, Syug-Ming Jang
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Patent number: 5976199Abstract: A manufacturing system for individually processing semiconductor wafers through a plurality of processing stations. The system has a plurality of processing stations, a multilevel track system that interfaces with the processing stations, and guided transport vehicles that operate on the track system to move individual wafers in wafer carriers between the stations. The carriers have a storage memory that contains the required process sequence and the capability to remember the completed process steps.Type: GrantFiled: February 14, 1997Date of Patent: November 2, 1999Assignee: United Microelectronics Corp.Inventors: Hong-Jen Wu, Taylor Chen, Jack Lai, I. I. Chen
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Patent number: 5842917Abstract: Operator-related contamination in a semiconductor manufacturing plant is reduced by eliminating operator presence in most of the processing areas of a semiconductor manufacturing plant. To facilitate the reduction of operator presence, the fabrication facility is divided into two physically separate areas. Operators are present in an inspection and testing area within the fabrication facility, and the processing equipment which is best used manually is located within this area. Processing equipment which does not require manual operation or monitoring and which performs particularly sensitive processing operations is located in one or more processing areas physically separated from the areas in which operators are present. Semiconductor wafer transport, processing and process monitoring within the processing areas is completely automated. Reduced volumes can be obtained for these processing chambers, allowing higher levels of cleanliness to be obtained in the sensitive processing areas.Type: GrantFiled: January 10, 1997Date of Patent: December 1, 1998Assignee: United Microelectronics CorprorationInventors: B. M. Soung, I. I. Chen
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Patent number: 5668056Abstract: A manufacturing system for individually processing semiconductor wafers through a plurality of processing stations. The system has a plurality of processing stations, a multilevel track system that interfaces with the processing stations, and guided transport vehicles that operate on the track system to move individual wafers in wafer carriers between the stations. The carriers have a storage memory that contains the required process sequence and the capability to remember the completed process steps.Type: GrantFiled: March 21, 1995Date of Patent: September 16, 1997Assignee: United Microelectronics CorporationInventors: Hong Jen Wu, Taylor Chen, Jack Lai, I. I. Chen