Abstract: Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.

Abstract: Disclosed is a method of debugging a simulation system including design code representing a design of an electronic circuit and test program code configured to exercise the design code. The method includes using an interactive debugging tool to execute an interactive simulation of the test program code and the design code, and, during the interactive simulation, displaying, using the interactive debugging tool, information of a simulation results file storing a plurality of signal values generated by executing the test program code and the design code during a previously executed simulation.

Abstract: A circuit for performing a residual side band calibration is described. The circuit generally includes a phase imbalance detection circuit. The phase imbalance detection circuit may include a limiter. The phase imbalance detection circuit may be independent of gain imbalance. The circuit may also include a phase imbalance correction circuit. The phase imbalance detection circuit may control coupling between an inphase path and a quadrature path.

Abstract: Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.

Abstract: A circuit for performing a residual side band calibration is described. The circuit generally includes a phase imbalance detection circuit. The phase imbalance detection circuit may include a limiter. The phase imbalance detection circuit may be independent of gain imbalance. The circuit may also include a phase imbalance correction circuit. The phase imbalance detection circuit may control coupling between an inphase path and a quadrature path.

Abstract: Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.

Abstract: Disclosed is a method of debugging a simulation system including design code representing a design of an electronic circuit and test program code configured to exercise the design code. The method includes using an interactive debugging tool to execute an interactive simulation of the test program code and the design code, and, during the interactive simulation, displaying, using the interactive debugging tool, information of a simulation results file storing a plurality of signal values generated by executing the test program code and the design code during a previously executed simulation.

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract: Power information associated with an IC design is displayed graphically and hierarchically using a power map, thereby providing an intuitive way for describing the power distribution among various power domains of the IC and parent-child relationships within the power domains. Each power domain is associated with a power control for controlling the power domain. The status of the power control for each power domain is displayed on the power map. The power map may include a token to set and display current operating mode of the IC design to enable the IC design to be debugged under different operating modes.

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract: A computer-implemented method for debugging the power aspect of an IC design by integrating the power specification expressed in certain power specification format and its corresponding circuit design within a power schematic diagram called power map. Power map is created by using a power data base generated by regrouping the original circuit design hierarchy to new hierarchies defined by the power specification. Power map contains power cell symbols (such as isolation cells, level shifters, power switches) and signal nets, and can show the relationship between power domains. Power map can also display mismatches or errors between the power specification and the circuit design for those signals connecting the power domains. Furthermore, power map can be used in conjunction with simulation result.

Abstract: Methods and apparatus for recording and visualizing transactions of a test bench simulation are disclosed. Transaction-specific data generated from a test bench simulation may be displayed in a sequence diagram view to provide a view of the transactions arranged sequentially in time.

Abstract: The internet bonding diagram system comprises a processing unit to process the information send by a user via a network. A blank lead frame/substrate database is coupled to the processing unit to store lead frame information. A job database is coupled to the processing unit to store information forwarded by a potential client, wherein the job database includes buyer satisfaction data provided by said user. A bonding diagram generator is coupled to the processing unit to generate a layout of bonding diagram in accordance with the information provided by the user. A forwarding module is responsive to the bonding diagram generator to forward the layout of bonding diagram to the user.

Abstract: An internet thermal data analysis system comprises a processing unit to process an information sent by a user via a network, wherein the information comprises a package information. A job database is coupled to the processing unit to store the package information sent by the user, a thermal analysis module is coupled to the processing unit to analysis the information sent by the user. A thermal data report generator is coupled to the processing unit to generate a thermal data simulation in accordance with the information sent by the user. A forwarding module is responsive to the thermal data report generator to forward the thermal data simulation to the user.

Abstract: An internet thermal data analysis system comprises a processing unit to process an information sent by a user via a network, wherein the information comprises a package information. A job database is coupled to the processing unit to store the package information sent by the user, a thermal analysis module is coupled to the processing unit to analysis the information sent by the user. A thermal data report generator is coupled to the processing unit to generate a thermal data simulation in accordance with the information sent by the user. A forwarding module is responsive to the thermal data report generator to forward the thermal data simulation to the user.

Abstract: The internet bonding diagram system comprises a processing unit to process the information send by a user via a network. A blank lead frame/substrate database is coupled to the processing unit to store lead frame information. A job database is coupled to the processing unit to store information forwarded by a potential client, wherein the job database includes buyer satisfaction data provided by said user. A bonding diagram generator is coupled to the processing unit to generate a layout of bonding diagram in accordance with the information provided by the user. A forwarding module is responsive to the bonding diagram generator to forward the layout of bonding diagram to the user.