Patents by Inventor I Lin

I Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250136668
    Abstract: The present disclosure relates to an antibody or antigen-binding fragment thereof that specifically binds to a spike protein of SARS-CoV-2. The present disclosure also relates to a pharmaceutical composition, a method for treating and/or preventing diseases and/or disorders caused by a coronavirus in a subject in need thereof, and a method for detecting a coronavirus in a sample.
    Type: Application
    Filed: November 8, 2024
    Publication date: May 1, 2025
    Inventors: Kuo-I LIN, Che MA, Chi-Huey WONG, Szu-Wen WANG, Yi-Hsuan CHANG, Xiaorui CHEN, Han-Yi HUANG
  • Publication number: 20250127506
    Abstract: A surgical device has a handle, a shaft connecting to the handle, a clamping portion disposed on one end of the shaft different from the end connected to the handle, a hook fixedly connected to the shaft and a closing member pivotally connected to the hook, and a control mechanism mounted on the handle and extending through the shaft and connect to the clamping portion, wherein the control mechanism controls the pivoting of the closing member to switch the clamping portion between a closed position and an opened position.
    Type: Application
    Filed: October 24, 2023
    Publication date: April 24, 2025
    Inventors: Yi Hsi Huang, I-Lin Tsai, Kuei-Hua Chen
  • Publication number: 20250126840
    Abstract: The present disclosure describes a semiconductor device having a source/drain dielectric. The semiconductor device includes a channel structure on a substrate, a dielectric structure on the substrate and adjacent to the channel structure, and an epitaxial structure on a top surface of the dielectric structure. The epitaxial structure is in contact with the channel structure.
    Type: Application
    Filed: February 6, 2024
    Publication date: April 17, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Cheng-Yu WEI, Cheng-I LIN, Shu-Han CHEN, Chi On CHUI
  • Patent number: 12274815
    Abstract: A method of preventing and handling indoor air pollution is disclosed and includes: providing a portable gas detection device and plural gas exchangers allowed to inhale outdoor gas, purify and filter the inhaled gas, and introduce the inhaled gas into the indoor space, wherein an air pollutant in the gas within the indoor space is exported out to the outdoor for exchanging; disposing 1˜50 gas exchangers within the indoor space, wherein the gas exchangers have an exported airflow rate of 200˜1600 CADR, and the indoor space has a volume of 247.5˜1650 m3; and remotely controlling the gas exchangers to enable filtration, purification and gas exchange by the portable gas detection device when the portable gas detection device detects an air pollutant in the indoor space, to reduce the air pollutant in the indoor space to a safe detection value within 10 minutes, and achieve a clean, safe and breathable condition.
    Type: Grant
    Filed: August 24, 2021
    Date of Patent: April 15, 2025
    Assignee: MICROJET TECHNOLOGY CO., LTD.
    Inventors: Hao-Jan Mou, Ching-Sung Lin, Chin-Chuan Wu, Chi-Feng Huang, Yung-Lung Han, Tsung-I Lin, Chin-Wen Hsieh
  • Publication number: 20250112363
    Abstract: An antenna structure includes a main ground element, an extension ground element, a feeding radiation element, a first radiation element, a second radiation element, a shorting radiation element, a third radiation element, and a dielectric substrate. The extension ground element is coupled to the main ground element. A notch region is defined by the main ground element and the extension ground element. The feeding radiation element has a feeding point. The first radiation element is coupled to the feeding radiation element. The second radiation element is coupled to the feeding radiation element. The second radiation element and the first radiation element substantially extend in opposite directions. The feeding radiation element is also coupled through the shorting radiation element to the extension ground element. The third radiation element is coupled to the main ground element.
    Type: Application
    Filed: November 2, 2023
    Publication date: April 3, 2025
    Inventors: Chun-I LIN, Bo-Wei LIN
  • Publication number: 20250092878
    Abstract: The invention relates to a control system, which is composed of a main controller electrically connected to an AC chopper wall-controller, enabling users to control the AC chopper wall-controller by pressing, and the AC chopper wall-controller fully utilizes the principle of AC electricity and combining it with the characteristics of AC zero-crossing circuit, the main controller that controls an electrical appliance is capable of easily identifying signals, and at the same time, signals of the main controller will not be interfered due to a short power outage, thus capable of working stably.
    Type: Application
    Filed: September 20, 2023
    Publication date: March 20, 2025
    Inventor: Chen I LIN
  • Publication number: 20250082744
    Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).
    Type: Application
    Filed: October 25, 2024
    Publication date: March 13, 2025
    Inventors: Chi-Huey WONG, Hsin-Yu LIAO, Shih-Chi WANG, Yi-An KO, Kuo-I LIN, Che MA, Ting-Jen CHENG
  • Publication number: 20250089330
    Abstract: A method includes forming a protruding fin, and forming a first dielectric layer including a first dielectric layer and a second dielectric layer over the first dielectric layer. The first dielectric layer includes a first top portion on a top surface of the protruding fin, and a sidewall portion on a sidewall of the protruding fin. The second dielectric layer is over the first top portion and the top surface of the protruding fin, and is formed using an anisotropic deposition process. The method further includes forming a dummy gate electrode on the second dielectric layer, forming a gate spacer on a sidewall of the dummy gate electrode, removing the dummy gate electrode, and forming a replacement gate electrode in a space left by the dummy gate electrode.
    Type: Application
    Filed: November 21, 2023
    Publication date: March 13, 2025
    Inventors: Cheng-Yu Wei, Cheng-I Lin, Hao-Ming Tang, Shu-Han Chen, Chi On Chui
  • Patent number: 12245872
    Abstract: The present disclosure provides an electronic device. The electronic device includes a flexible element, and a sensing element adjacent to the flexible element and configured to detect a biosignal. The electronic device also includes an active component in the flexible element and electrically connected with the sensing element. A method of manufacturing an electronic device is also disclosed.
    Type: Grant
    Filed: April 29, 2021
    Date of Patent: March 11, 2025
    Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.
    Inventors: Chih Lung Lin, Kuei-Hao Tseng, Te Kao Tsui, Kai Hung Wang, Hung-I Lin
  • Patent number: 12243786
    Abstract: An embodiment includes a device including a first semiconductor fin extending from a substrate, a second semiconductor fin extending from the substrate, a hybrid fin over the substrate, the hybrid fin disposed between the first semiconductor fin and the second semiconductor fin, and the hybrid fin having an oxide inner portion extending downward from a top surface of the hybrid fin. The device also includes a first isolation region between the second semiconductor fin, the first semiconductor fin, and the hybrid fin, the hybrid fin extending above a top surface of the first isolation region, a high-k gate dielectric over sidewalls of the hybrid fin, sidewalls of the first semiconductor fin, and sidewalls of the second semiconductor fin, a gate electrode on the high-k gate dielectric, and source/drain regions on the first semiconductor fin on opposing sides of the gate electrode.
    Type: Grant
    Filed: May 13, 2022
    Date of Patent: March 4, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Cheng-I Lin, Da-Yuan Lee, Chi On Chui
  • Patent number: 12243872
    Abstract: A semiconductor device structure, along with methods of forming such, are described. The structure includes a first channel region disposed over a substrate, a second channel region disposed adjacent the first channel region, a gate electrode layer disposed in the first and second channel regions, and a first dielectric feature disposed adjacent the gate electrode layer. The first dielectric feature includes a first dielectric material having a first thickness. The structure further includes a second dielectric feature disposed between the first and second channel regions, and the second dielectric feature includes a second dielectric material having a second thickness substantially less than the first thickness. The second thickness ranges from about 1 nm to about 20 nm.
    Type: Grant
    Filed: February 15, 2022
    Date of Patent: March 4, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chen-Huang Huang, Yu-Ling Cheng, Shun-Hui Yang, An Chyi Wei, Chia-Jen Chen, Shang-Shuo Huang, Chia-I Lin, Chih-Chang Hung
  • Publication number: 20250048753
    Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material. A second semiconductor material is disposed on the substrate. A doped region is between the substrate and a part of the second semiconductor material. The second semiconductor material includes a projection extending outward from a surface of the second semiconductor material and towards the photodiode region. The projection extends through the doped region.
    Type: Application
    Filed: October 23, 2024
    Publication date: February 6, 2025
    Inventors: Yung-Chang Chang, Shih-Wei Lin, Te-Hsien Hsieh, Jung-I Lin
  • Publication number: 20250048703
    Abstract: Semiconductor devices and methods of manufacture are presented. In embodiments a method of manufacturing the semiconductor device includes forming a fin from a plurality of semiconductor materials, depositing a dummy gate over the fin, depositing a plurality of spacers adjacent to the dummy gate, removing the dummy gate to form an opening adjacent to the plurality of spacers, widening the opening adjacent to a top surface of the plurality of spacers, after the widening, removing one of the plurality of semiconductor materials to form nanowires, and depositing a gate electrode around the nanowires.
    Type: Application
    Filed: October 19, 2023
    Publication date: February 6, 2025
    Inventors: Cheng-Yu Wei, Hao-Ming Tang, Cheng-I Lin, Shu-Han Chen, Chi On Chui
  • Publication number: 20250048725
    Abstract: A semiconductor device structure and methods of forming the same are described. The structure includes a first semiconductor layer disposed over a substrate, the first semiconductor layer has an edge portion and a center portion, and a height of the center portion is substantially greater than a height of the edge portion. The structure further includes a dielectric spacer disposed below and in contact with the edge portion of the first semiconductor layer, a gate dielectric layer surrounding the center portion of the first semiconductor layer, and a gate electrode layer disposed on the gate dielectric layer surrounding the center portion of the first semiconductor layer.
    Type: Application
    Filed: October 17, 2023
    Publication date: February 6, 2025
    Inventors: Cheng-I LIN, Shu-Han CHEN, Chi On CHUI
  • Patent number: 12205743
    Abstract: A modularized transformer includes an annular iron core, a first module encircling the annular iron core, a second module encircling the first module, a third module encircling the second module, a fourth module encircling the third module, and a primary-side power supply line mounted on the fourth module and encircling the annular iron core. Thus, the modularized transformer has a modularized structure and includes multiple modules that are extended and increased to amplify the voltage or current continuously and to regulate the voltage or current.
    Type: Grant
    Filed: January 10, 2022
    Date of Patent: January 21, 2025
    Inventor: Hsun-I Lin
  • Patent number: 12198974
    Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a trench in a substrate. A liner layer is formed along sidewalls and a bottom of the trench. A silicon-rich layer is formed over the liner layer. Forming the silicon-rich layer includes flowing a first silicon precursor into a process chamber for a first time interval, and flowing a second silicon precursor and a first oxygen precursor into the process chamber for a second time interval. The second time interval is different from the first time interval. The method further includes forming a dielectric layer over the silicon-rich layer.
    Type: Grant
    Filed: July 13, 2023
    Date of Patent: January 14, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Cheng-I Lin, Bang-Tai Tang
  • Publication number: 20250006829
    Abstract: A method includes alternately stacking first semiconductor layers and second semiconductor layers over a substrate, patterning the first and second semiconductor layers into a fin structure, forming a dummy gate structure across the fin structure, depositing gate spacers over sidewalls of the dummy gate structure, removing the dummy gate structure to form a recess, removing the first semiconductor layers, depositing an interfacial layer wrapping the second semiconductor layers, depositing a high-k dielectric layer over the interfacial layer and over the sidewalls of the gate spacers, depositing a first gate electrode over the high-k dielectric layer, recessing the first gate electrode and the high-k dielectric layer to expose a top portion of the sidewalls of the gate spacers, depositing a low-k dielectric layer over the recessed high-k dielectric layer, and depositing a second gate electrode over the first gate electrode.
    Type: Application
    Filed: October 17, 2023
    Publication date: January 2, 2025
    Inventors: Cheng-I Lin, Shu-Han Chen, Chi On Chui
  • Patent number: 12178870
    Abstract: The present disclosure relates to a chimeric influenza virus hemagglutinin (HA) polypeptide, comprising one or more stem domain sequence, each having at least 60% homology with a stem domain consensus sequence of H1 subtype HA (H1 HA) and/or H5 subtype HA (H5 HA), fused with one or more globular head domain sequence, each having at least 60% homology with a globular head domain consensus sequence of H1 subtype HA (H1 HA) or H5 subtype HA (H5 HA).
    Type: Grant
    Filed: May 13, 2024
    Date of Patent: December 31, 2024
    Assignee: Academia Sinica
    Inventors: Chi-Huey Wong, Hsin-Yu Liao, Shih-Chi Wang, Yi-An Ko, Kuo-I Lin, Che Ma, Ting-Jen Cheng
  • Patent number: 12183764
    Abstract: The present disclosure relates to an image sensor integrated chip. The image sensor integrated chip includes a photodiode region disposed within a substrate having a first semiconductor material region. A second semiconductor material region is disposed onto the substrate. A patterned doped layer is arranged between the substrate and the second semiconductor material region. The second semiconductor material region includes a sidewall connecting to a bottom surface of the second semiconductor material region. The sidewall extends through the patterned doped layer. A bottom surface of the second semiconductor material region is directly over the photodiode region.
    Type: Grant
    Filed: May 3, 2022
    Date of Patent: December 31, 2024
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yung-Chang Chang, Shih-Wei Lin, Te-Hsien Hsieh, Jung-I Lin
  • Patent number: D1060763
    Type: Grant
    Filed: May 5, 2023
    Date of Patent: February 4, 2025
    Assignee: Kuen Hwa Traffic Industrial Co., Ltd.
    Inventor: Chung-I Lin