Abstract: A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.

Abstract: A method and apparatus for performing access control of a memory device with aid of a multi-phase memory-mapped queue are provided. The method includes: receiving a first host command from a host device; and in response to the first host command, utilizing a processing circuit within the controller to send a first operation command to the NV memory through a control logic circuit of the controller, and trigger a first set of secondary processing circuits within the controller to operate and interact via the multi-phase memory-mapped queue, for accessing the first data for the host device, wherein the processing circuit and the first set of secondary processing circuits share the multi-phase memory-mapped queue, and use the multi-phase memory-mapped queue as multiple chained message queues associated with multiple phases, respectively, for performing message queuing for a chained processing architecture including the processing circuit and the first set of secondary processing circuits.

Abstract: A data storage device includes at least one non-volatile memory and a controller with two-layer architecture. The two-layer architecture includes a front end coupled to a host and a back end coupled to the non-volatile memory. The controller includes a command processor and at least one non-volatile memory controller. The command processor is arranged on the front end to communicate with the host, and it schedules the operation of the data storage device based on an external command from the host. The non-volatile memory controller is arranged on the back end, and it controls the non-volatile memory based on the schedule of the command processor. When the non-volatile memory increases, the non-volatile memory controller also increases correspondingly while the amount of command processors remains the same.

Abstract: A data storage device includes at least one non-volatile memory and a controller with two-layer architecture. The two-layer architecture includes a front end coupled to a host and a back end coupled to the non-volatile memory. The controller includes a command processor and at least one non-volatile memory controller. The command processor is arranged on the front end to communicate with the host, and it schedules the operation of the data storage device based on an external command from the host. The non-volatile memory controller is arranged on the back end, and it controls the non-volatile memory based on the schedule of the command processor. When the non-volatile memory increases, the non-volatile memory controller also increases correspondingly while the amount of command processors remains the same.