Patents by Inventor I Liu
I Liu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Publication number: 20250079853Abstract: A power generating device and a power supplying method thereof are provided. The power generating device includes a battery set, a charge storage device, a charger and a voltage converter. The battery set has microbial fuel cell and/or solar battery, and is configured to generate a supply voltage. The charger generates a charging voltage according to the supply voltage, and provides the charging voltage through a first resistor to charge the charge storage device. The voltage converter converts a storage voltage provided by the charge storage device to generate a driving voltage, and provides the driving voltage to drive a load.Type: ApplicationFiled: October 20, 2023Publication date: March 6, 2025Applicant: National Tsing Hua UniversityInventors: Chao-I Liu, Heng-An Su, I-Chu Lin, Yao-Yu Lin, Chia-Chieh Hsu, Hsin-Tien Li, Tzu-Yin Liu, Han-Yi Chen
-
Publication number: 20240395609Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.Type: ApplicationFiled: July 31, 2024Publication date: November 28, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsiao-Min CHEN, Jyh-Nan LIN, Kai-Shiung HSU, Ding-I LIU
-
Patent number: 12154608Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.Type: GrantFiled: August 8, 2023Date of Patent: November 26, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
-
Publication number: 20240384404Abstract: The present disclosure describes a semiconductor device manufacturing apparatus and a method for handling contamination in the semiconductor device manufacturing apparatus. The semiconductor device manufacturing apparatus can include a deposition apparatus and a processor. The deposition apparatus can include a chamber, a detection module configured to detect impurities in the chamber, and a gas scrubbing device configured to remove the impurities. The processor can be configured to receive, from the detection module, an impurity characteristic associated with the impurities; compare the impurity characteristic to a baseline characteristic; and instruct the gas scrubbing device to supply a decontamination gas in the chamber based on the comparison of the impurity characteristic to the baseline characteristic.Type: ApplicationFiled: July 30, 2024Publication date: November 21, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jia-Wei XU, Ding-I Liu, Kai-Shiung Hsu, Yin-Bin Tseng
-
Patent number: 12148656Abstract: In a method of manufacturing a semiconductor device, a first dielectric layer is formed over a substrate, an adhesion enhancement layer is formed on a surface of the first dielectric layer, and a second dielectric layer is formed on the adhesion enhancement layer.Type: GrantFiled: May 2, 2022Date of Patent: November 19, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hsiao-Min Chen, Jyh-Nan Lin, Kai-Shiung Hsu, Ding-I Liu
-
Publication number: 20240312792Abstract: A method of manufacturing a semiconductor device includes forming a gate dielectric layer over a channel region, and forming a first conductive layer over the gate dielectric layer. The method further includes forming a protective layer at a surface region of the first conductive layer by implanting a dopant into the surface region of the first conductive layer. The dopant is selected from a group consisting of boron, silicon, carbon, and nitrogen. The method also includes forming a metallic layer by applying a metal containing gas on the protective layer, and removing the metallic layer by a wet etching operation using a solution.Type: ApplicationFiled: May 22, 2024Publication date: September 19, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hui-An HAN, Ding-I LIU, Yuh-Ta FAN, Kai-Shiung HSU
-
Publication number: 20240258160Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: ApplicationFiled: March 19, 2024Publication date: August 1, 2024Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
-
Publication number: 20240220055Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.Type: ApplicationFiled: March 19, 2024Publication date: July 4, 2024Inventors: Chen-Cheng LIN, Chia-I LIU, Kun-Hsien LEE, Hung-Wei TSENG
-
Patent number: 12020947Abstract: In a method of manufacturing a semiconductor device, a gate dielectric layer is formed over a channel region, a first conductive layer is formed over the gate dielectric layer, a protective layer is formed at a surface region of the first conductive layer, a metallic layer is formed by applying a metal containing gas on the protective layer, and the metallic layer is removed by a wet etching operation using a solution. The protective layer is resistant to the solution of the wet etching operation.Type: GrantFiled: July 19, 2021Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Hui-An Han, Ding-I Liu, Yuh-Ta Fan, Kai-Shiung Hsu
-
Patent number: 12020905Abstract: A method of making a semiconductor device includes comparing a thickness profile of a surface of a wafer with a reference value using a control unit. The method further includes transmitting a control signal to an adjustable nozzle based on the comparison of the thickness profile and the reference value. The method further includes rotating the adjustable nozzle about a longitudinal axis of the adjustable nozzle in response to the control signal.Type: GrantFiled: May 9, 2022Date of Patent: June 25, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Wei-Ching Wu, Ding-I Liu, Wen-Long Lee
-
Patent number: 11990167Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.Type: GrantFiled: June 21, 2021Date of Patent: May 21, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
-
Patent number: 11966546Abstract: A display device includes a base layer, a touch sensing layer, a light guide module and a display panel. The touch sensing layer is disposed on the base layer. The light guide module is disposed on the touch sensing layer. The touch sensing layer is located between the light guide module and the display panel, and the touch sensing layer and one of the light guide module and the display panel have no adhesive material therebetween.Type: GrantFiled: August 19, 2021Date of Patent: April 23, 2024Assignee: E Ink Holdings Inc.Inventors: Chen-Cheng Lin, Chia-I Liu, Kun-Hsien Lee, Hung-Wei Tseng
-
Patent number: 11967522Abstract: A method includes depositing an etch stop layer over a first conductive feature, performing a first treatment to amorphize the etch stop layer, depositing a dielectric layer over the etch stop layer, etching the dielectric layer to form an opening, etching-through the etch stop layer to extend the opening into the etch stop layer, and filling the opening with a conductive material to form a second conductive feature.Type: GrantFiled: April 25, 2022Date of Patent: April 23, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Jyh-Nan Lin, Chia-Yu Wu, Kai-Shiung Hsu, Ding-I Liu
-
Patent number: 11967272Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.Type: GrantFiled: December 9, 2022Date of Patent: April 23, 2024Assignees: AUO Corporation, National Cheng-Kung UniversityInventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
-
Publication number: 20240029630Abstract: A sweep voltage generator and a display panel are provided. The sweep voltage generator includes an output node, a current generating block and a voltage regulating block. The output node is used to provide a sweep signal. The current generating block is coupled to the output node, includes a detection path for detecting an output load variation on the output node, and adjusts the sweep signal provided by the output node based on the output load variation. The voltage regulating block is coupled to the output node for regulating a voltage of the output node.Type: ApplicationFiled: December 9, 2022Publication date: January 25, 2024Applicants: AUO Corporation, National Cheng-Kung UniversityInventors: Chih-Lung Lin, Yi-Chen Huang, Chih-I Liu, Po-Cheng Lai, Ming-Yang Deng, Chia-En Wu, Ming-Hung Chuang, Chia-Tien Peng
-
Publication number: 20240021230Abstract: A semiconductor device and a method of forming the same are provided. The method includes forming a bottom electrode layer over a substrate. A magnetic tunnel junction (MTJ) layers are formed over the bottom electrode layer. A top electrode layer is formed over the MTJ layers. The top electrode layer is patterned. After patterning the top electrode layer, one or more process cycles are performed on the MTJ layers and the bottom electrode layer. A patterned top electrode layer, patterned MTJ layers and a patterned bottom electrode layer form MTJ structures. Each of the one or more process cycles includes performing an etching process on the MTJ layers and the bottom electrode layer for a first duration and performing a magnetic treatment on the MTJ layers and the bottom electrode layer for a second duration.Type: ApplicationFiled: August 8, 2023Publication date: January 18, 2024Inventors: Bo-Jhih Shen, Kuang-I Liu, Joung-Wei Liou, Jinn-Kwei Liang, Yi-Wei Chiu, Chin-Hsing Lin, Li-Te Hsu, Han-Ting Tsai, Cheng-Yi Wu, Shih-Ho Lin
-
Patent number: 11872163Abstract: A magnetic positioning system and related method for automated or assisted eye-docking in ophthalmic surgery. The system includes a magnetic field sensing system on a laser head and a magnet on a patient interface to be mounted on the patient's eye. The magnetic field sensing system includes four magnetic field sensors located on a horizontal plane for detecting the magnetic field of the magnet, where one pair of sensors are located along the X direction at equal distances from the optical axis of the laser head and another pair are located along the Y direction at equal distances from the optical axis. Based on relative magnitudes of the magnetic field detected by each pair of sensors, the magnetic field sensing system determines whether the patient interface is centered on the optical axis. The system controls the laser head to move toward the patient interface until the latter is centered on the optical axis.Type: GrantFiled: December 22, 2021Date of Patent: January 16, 2024Assignee: AMO Development, LLCInventors: Harvey I. Liu, John P. Beale
-
Patent number: 11865044Abstract: An RF (radio frequency) positioning system and related method for automated or assisted eye-docking in ophthalmic surgery. The system includes an RF detector system on a laser head and an RFID tag on a patient interface to be mounted on the patient's eye. The detector system includes four RF antennas located on a horizontal plane for detecting RF signals from the RFID tag, where one pair of antennas are located along the X direction at equal distances from the optical axis of the laser head and another pair are located along the Y direction at equal distances from the optical axis. Based on relative strengths and phase difference of the RF signals detected by each pair of antennas, the RF detector system determines whether the patient interface is centered on the optical axis. The RF detector system controls the laser head to move toward the patient interface until the latter is centered on the optical axis.Type: GrantFiled: July 6, 2022Date of Patent: January 9, 2024Assignee: AMO Development, LLCInventors: Harvey I. Liu, John P. Beale, Jose L. Garcia
-
Publication number: 20230377955Abstract: A method for improving reliability of interconnect structures for semiconductor devices is disclosed. The method includes forming a contact structure on a transistor and forming a metallization layer on the contact structure. The forming the metallization layer includes depositing an inter-metal dielectric (IMD) layer on the transistor, forming an opening within the IMD layer to expose a top surface of the contact structure, depositing a metallic layer to fill the opening, forming an electron barrier layer within the IMD layer, and forming a capping layer within the metallic layer. The electron barrier layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the IMD layer underlying the electron barrier layer. The capping layer has a hole carrier concentration higher than a hole carrier concentration of a portion of the metallic layer underlying the capping layer.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Chun-Jen CHEN, Kai-Shiung Hsu, Ding-I Liu, Jyh-nan Lin
-
Publication number: 20230317827Abstract: Some embodiments provide a process of tunning sidewall profiles of gate openings prior to filling a replacement gate electrode layer therein to improve etching rate uniformity and stability during a subsequent gate electrode etch back process. Particularly, the profile sacrificial gate electrode is adjusted to be more straight profile rather than a bowl type profile, which reduces the seam void created in the replacement gate electrode during the replacement gate process. In some embodiments, tuning the profile of gate opening further includes performing a pullback etching process of the sidewall spacers prior to depositing gate dielectric layer and work function metal layer to achieve a wider opening for metal gate filling in the replacement gate process.Type: ApplicationFiled: August 18, 2022Publication date: October 5, 2023Inventors: Chi-Ming HUANG, Chun-I LIU, Yu-Li LIN, Chih-Lun LU, Chen-Wei PAN, Chih-Teng LIAO