Patents by Inventor I-Lu Wu
I-Lu Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8237209Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate.Type: GrantFiled: August 23, 2011Date of Patent: August 7, 2012Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Long Chang, David Ding-Chung Lu, Chia-Yi Chen, I-Lu Wu
-
Publication number: 20110309420Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate and a MIM capacitor over the substrate. The MIM capacitor includes a bottom plate, an insulating layer over the bottom plate, and a top plate over the insulating layer. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate and a metal-containing gate electrode free from polysilicon on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material and has a same thickness as the bottom plate.Type: ApplicationFiled: August 23, 2011Publication date: December 22, 2011Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Long Chang, David Ding-Chung Lu, Chia-Yi Chen, I-Lu Wu
-
Patent number: 8022458Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.Type: GrantFiled: October 8, 2007Date of Patent: September 20, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Long Chang, David Ding-Chung Lu, Chia-Yi Chen, I-Lu Wu
-
Patent number: 7986029Abstract: A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively. A first region of the second semiconductor layer is replaced with an epitaxially grown layer of the first semiconductor layer, thereby providing a substrate having a first region with a first crystal orientation and a second region with a second crystal orientation. An isolation structure is formed to isolate the first and second regions. Thereafter, NMOS and PMOS transistors may be formed on the substrate in the region having the crystal orientation that is the most appropriate.Type: GrantFiled: November 8, 2005Date of Patent: July 26, 2011Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chiang-Ming Chuang, Kuang-Hsin Chen, I-Lu Wu
-
Patent number: 7611937Abstract: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.Type: GrantFiled: November 17, 2005Date of Patent: November 3, 2009Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Chung-Te Lin, I-Lu Wu, Mariam Sadaka
-
Publication number: 20090090951Abstract: A semiconductor structure including a capacitor having increased capacitance and improved electrical performance is provided. The semiconductor structure includes a substrate; and a capacitor over the substrate. The capacitor includes a first layer including a first capacitor electrode and a second capacitor electrode, wherein the first capacitor electrode is formed of a metal-containing material and is free from polysilicon. The semiconductor structure further includes a MOS device including a gate dielectric over the substrate; and a metal-containing gate electrode on the gate dielectric, wherein the metal-containing gate electrode is formed of a same material, and has a same thickness, as the first capacitor electrode.Type: ApplicationFiled: October 8, 2007Publication date: April 9, 2009Inventors: Chung-Long Chang, David Ding-Chung Lu, Chia-Yi Chen, I-Lu Wu
-
Patent number: 7432149Abstract: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the <100> direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the <110> direction, which is the direction where hole mobility is maximum for a {110} substrate.Type: GrantFiled: November 30, 2005Date of Patent: October 7, 2008Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Lu Wu, Chung-Te Lin, Tan-Chen Lee
-
Patent number: 7297587Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.Type: GrantFiled: January 3, 2007Date of Patent: November 20, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Lu Wu, Kuang-Hsin Chen, Liang-Kai Han
-
Publication number: 20070111425Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.Type: ApplicationFiled: January 3, 2007Publication date: May 17, 2007Inventors: I-Lu Wu, Kuang-Hsin Chen, Liang-Kai Han
-
Publication number: 20070102769Abstract: A semiconductor structure having a hybrid crystal orientation is provided. The semiconductor structure includes an insulator layer, e.g., a buried oxide (BOX), on a first semiconductor layer, and a second semiconductor layer on the buried oxide, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively. A first region of the second semiconductor layer is replaced with an epitaxially grown layer of the first semiconductor layer, thereby providing a substrate having a first region with a first crystal orientation and a second region with a second crystal orientation. An isolation structure is formed to isolate the first and second regions. Thereafter, NMOS and PMOS transistors may be formed on the substrate in the region having the crystal orientation that is the most appropriate.Type: ApplicationFiled: November 8, 2005Publication date: May 10, 2007Inventors: Chiang-Ming Chuang, Kuang-Hsin Chen, I-Lu Wu
-
Patent number: 7183596Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.Type: GrantFiled: June 22, 2005Date of Patent: February 27, 2007Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: I-Lu Wu, Kuang-Hsin Chen, Liang-Kai Han
-
Publication number: 20060289920Abstract: An integrated circuit having composite gate structures and a method of forming the same are provided. The integrated circuit includes a first MOS device, a second MOS device and a third MOS device. The gate stack of the first MOS device includes a high-k gate dielectric and a first metal gate on the high-k gate dielectric. The gate stack of the second MOS device includes a second metal gate on a high-k gate dielectric. The first metal gate and the second metal gate have different work functions. The gate stack of the third MOS device includes a silicon gate over a gate dielectric. The silicon gate is preferably formed over the gate stacks of the first MOS device and the second MOS device.Type: ApplicationFiled: June 22, 2005Publication date: December 28, 2006Inventors: I-Lu Wu, Kuang-Hsin Chen, Liang-Kai Han
-
Publication number: 20060292834Abstract: A method of forming a semiconductor structure having a hybrid crystal orientation and forming MOSFETs having improved performance on the semiconductor structure is provided. The method includes providing a substrate comprising a buried oxide (BOX) on a first semiconductor layer, and a second semiconductor layer on the BOX, wherein the first and second semiconductor layers have a first and a second crystal orientation, respectively, and wherein the substrate comprises a first region and a second region. An isolation structure is formed in the second region extending to the first semiconductor layer. A trench is then formed in the isolation structure, exposing the first semiconductor layer. A semiconductor material is epitaxially grown in the trench. The method further includes forming a MOSFET of a first type on the second semiconductor layer and a MOSFET of an opposite type than the first type on the epitaxially grown semiconductor material.Type: ApplicationFiled: November 17, 2005Publication date: December 28, 2006Inventors: Chung-Te Lin, I-Lu Wu, Mariam Sadaka
-
Publication number: 20060292770Abstract: Methods and structures for CMOS devices with hybrid crystal orientations using double SOI substrates is provided. In accordance with preferred embodiments, a manufacturing sequence includes the steps of forming an SOI silicon epitaxy layer after the step of forming shallow trench isolation regions. The preferred sequence allows hybrid SOI CMOS fabrication without encountering problems caused by forming STI regions after epitaxy. A preferred device includes an NFET on a {100} crystal orientation and a PFET on a {110} crystal orientation. An NMOS channel may be oriented along the <100> direction, which is the direction of maximum electron mobility for a {100} substrate. A PMOS channel may be oriented along the <110> direction, which is the direction where hole mobility is maximum for a {110} substrate.Type: ApplicationFiled: November 30, 2005Publication date: December 28, 2006Inventors: I-Lu Wu, Chung-Te Lin, Tan-Chen Lee