Abstract: A herbal extract for anemia is obtained by a process including steps of drying, by providing a herbal material comprising dry mulberry and dry Acanthopanax senticosus in a weight ratio of 2:1 to 1:2, with the water content of the herbal material lower than 10%; extracting, by soaking the herbal material into a solvent to obtain a liquid extract, with the weight ratio between the herbal material and the solvent being 1:10 to 1:5; and condensation, by condensing the liquid extract to obtain a herbal extract.

Abstract: In the present invention, a ginger extract for inhibiting the fat-storage function of adipocytes and a medication thereof is disclosed, wherein the ginger extract is obtained form Alpinia galangal and Zingiber zerumbet.

Abstract: A herbal extract for anemia is obtained by a process including steps of drying, by providing a herbal material comprising dry mulberry and dry Acanthopanax senticosus in a weight ratio of 2:1 to 1:2, with the water content of the herbal material lower than 10%; extracting, by soaking the herbal material into a solvent to obtain a liquid extract, with the weight ratio between the herbal material and the solvent being 1:10 to 1:5; and condensation, by condensing the liquid extract to obtain a herbal extract.

Abstract: A manufacture method of microcapsule, comprises a step of extraction, by extracting active substance from a sample of Chinese angelica and obtaining an extract; a step of encapsulation, by encapsulating the extract with a covering, wherein the extract and the covering are mixed and co-dropped in a solidified solution for solidifying the covering, and the extract is encapsulated in the solidified covering to obtain a microcapsule; and a step of drying, by drying and finalizing the microcapsule.

Abstract: An integrated circuit (IC) layout system designs nets for interconnecting cells forming modules of a hierarchical IC design. Each module is defined as having one or more ports through which the nets extend when linking cells forming different modules. The layout system automatically inserts buffers into selected segments of the nets to reduce signal path delays through the nets and assigns the inserted buffers to selected modules. However the layout system inserts buffers only into those net segments for which a buffer insertion would not alter the number of ports any module needs to accommodate the net.

Abstract: An integrated circuit design includes a description of a net for distributing a signal from a root node to one or more leaf nodes downstream of the root node. Some segments of the net include inverters and some segments branch into other segments. The IC design is processed to determine a maximum number of inverters that can be removed from the net without affecting a logic state of the signal as it arrives at the leaf nodes. For each segment of the net other than segments terminating on root or leaf nodes two corresponding data sets are generated: one data set indicates a maximum number of inverters that may be removed downstream of its corresponding segment without altering the logic state of the signal at any downstream leaf node, and the other data set indicates a maximum number of downstream inverters that may be removed that will alter the logic state of the signal arriving at every downstream leaf node.

Abstract: An integrated circuit design includes a description of a net for distributing a signal from a root node to one or more leaf nodes downstream of the root node. Some segments of the net include inverters and some segments branch into other segments. The IC design is processed to determine a maximum number of inverters that can be removed from the net without affecting a logic state of the signal as it arrives at the leaf nodes. For each segment of the net other than segments terminating on root or leaf nodes two corresponding data sets are generated: one data set indicates a maximum number of inverters that may be removed downstream of its corresponding segment without altering the logic state of the signal at any downstream leaf node, and the other data set indicates a maximum number of downstream inverters that may be removed that will alter the logic state of the signal arriving at every downstream leaf node.