Patents by Inventor I-Ming Lai
I-Ming Lai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11923205Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: GrantFiled: December 17, 2021Date of Patent: March 5, 2024Assignee: UNITED MICROELECTRONICS CORPORATIONInventors: Kun-Ju Li, Ang Chan, Hsin-Jung Liu, Wei-Xin Gao, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-Ming Lai, Fu-Shou Tsai
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Publication number: 20240055401Abstract: A semiconductor assembly and a method for manufacturing the same are provided. The semiconductor assembly includes a first substrate, a first well in the first substrate and having a first doping type, a second substrate, a second well in the second substrate and having a second doping type, a first dielectric layer between the first substrate and the second substrate, and a second dielectric layer between the first substrate and the second substrate. The first doping type is different from the second doping type. The second dielectric layer is bonded to the first dielectric layer. The first well overlaps with the second well in a vertical direction.Type: ApplicationFiled: September 8, 2022Publication date: February 15, 2024Inventors: Kun-Ju LI, Hsin-Jung LIU, Zong-Sian WU, Wei-Xin GAO, Jhih-Yuan CHEN, Ang CHAN, Chau-Chung HOU, Hsiang-Chi CHIEN, I-Ming LAI
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Publication number: 20230197467Abstract: A method for manufacturing a semiconductor device includes: providing a wafer-bonding stack structure having a sidewall layer and an exposed first component layer; forming a photoresist layer on the first component layer; performing an edge trimming process to at least remove the sidewall layer; and removing the photoresist layer. In this way, contaminant particles generated from the blade during the edge trimming process may fall on the photoresist layer but not fall on the first component layer, so as to protect the first component layer from being contaminated.Type: ApplicationFiled: December 17, 2021Publication date: June 22, 2023Inventors: KUN-JU LI, Ang Chan, HSIN-JUNG LIU, WEI-XIN GAO, Jhih-Yuan Chen, Chun-Han Chen, Zong-Sian Wu, Chau-Chung Hou, I-MING LAI, FU-SHOU TSAI
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Patent number: 8921206Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.Type: GrantFiled: November 30, 2011Date of Patent: December 30, 2014Assignee: United Microelectronics Corp.Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
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Publication number: 20140191285Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant. The epitaxial structures and the undoped cap layer include a first semiconductor material having a first lattice constant and a second semiconductor material having a second lattice constant. The second lattice constant is larger than the first lattice constant. The second semiconductor material in the epitaxial structure includes a first concentration and the second semiconductor material in the undoped cap layer includes a second concentration. The second concentration is lower than the first concentration, and is upwardly decreased.Type: ApplicationFiled: March 11, 2014Publication date: July 10, 2014Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chin-I Liao, Teng-Chun Hsuan, I-Ming Lai, Chin-Cheng Chien
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Patent number: 8716750Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.Type: GrantFiled: July 25, 2011Date of Patent: May 6, 2014Assignee: United Microelectronics Corp.Inventors: Chin-I Liao, Teng-Chun Hsuan, I-Ming Lai, Chin-Cheng Chien
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Patent number: 8710632Abstract: A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.Type: GrantFiled: September 7, 2012Date of Patent: April 29, 2014Assignee: United Microelectronics Corp.Inventors: Tien-Wei Yu, Chin-Cheng Chien, I-Ming Lai, Shin-Chi Chen, Chih-Yueh Li, Fong-Lung Chuang, Chin-I Liao, Kuan-Yu Lin
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Publication number: 20140070377Abstract: A method for fabricating a compound semiconductor epitaxial structure includes the following steps. Firstly, a first compound epitaxial layer is formed on a substrate. Then, a continuous epitaxial deposition process is performed to form a second compound epitaxial layer on the first compound epitaxial layer, so that the second compound epitaxial layer has a linearly-decreased concentration gradient of metal. Afterwards, a semiconductor material layer is formed on the second compound epitaxial layer.Type: ApplicationFiled: September 7, 2012Publication date: March 13, 2014Applicant: UNITED MICROELECTRONICS CORPORATIONInventors: Tien-Wei YU, Chin-Cheng CHIEN, I-Ming LAI, Shin-Chi CHEN, Chih-Yueh LI, Fong-Lung CHUANG, Chin-I LIAO, Kuan-Yu LIN
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Patent number: 8647953Abstract: A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.Type: GrantFiled: November 17, 2011Date of Patent: February 11, 2014Assignee: United Microelectronics Corp.Inventors: Chin-I Liao, I-Ming Lai, Chin-Cheng Chien
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Patent number: 8519390Abstract: A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.Type: GrantFiled: July 25, 2011Date of Patent: August 27, 2013Assignee: United Microelectronics Corp.Inventors: Chin-I Liao, Teng-Chun Hsuan, I-Ming Lai, Chin-Cheng Chien
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Publication number: 20130137243Abstract: First, a substrate with a recess is provided in a semiconductor process. Second, an embedded SiGe layer is formed in the substrate. The embedded SiGe layer includes an epitaxial SiGe material which fills up the recess. Then, a pre-amorphization implant (PAI) procedure is carried out on the embedded SiGe layer to form an amorphous region. Next, a source/drain implanting procedure is carried out on the embedded SiGe layer to form a source doping region and a drain doping region. Later, a source/drain annealing procedure is carried out to form a source and a drain in the substrate. At least one of the pre-amorphization implant procedure and the source/drain implanting procedure is carried out in a cryogenic procedure below ?30° C.Type: ApplicationFiled: November 30, 2011Publication date: May 30, 2013Inventors: Chan-Lon Yang, Ching-I Li, Ger-Pin Lin, I-Ming Lai, Yun-San Huang, Chin-I Liao, Chin-Cheng Chien
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Publication number: 20130126949Abstract: A method for fabricating a metal oxide semiconductor (MOS) device is described, including following steps. Two recesses are formed in a substrate. A first epitaxy growth process is performed, so as to form a first semiconductor compound layer in each of the recesses. A second epitaxy growth process is performed with an epitaxial temperature lower than 700° C., so as to form a cap layer on each of the first semiconductor compound layers. Each of the cap layers includes a second semiconductor compound layer protruding from a surface of the substrate. The first and the second semiconductor compound layers are composed of a first Group IV element and a second Group IV element, wherein the second Group IV element is a nonsilicon element. The content of the second Group IV element in the second semiconductor compound layers is less than that in the first semiconductor compound layers.Type: ApplicationFiled: November 17, 2011Publication date: May 23, 2013Applicant: UNITED MICROELECTRONICS CORP.Inventors: Chin-I Liao, I-Ming Lai, Chin-Cheng Chien
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Patent number: 8445363Abstract: A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.Type: GrantFiled: April 21, 2011Date of Patent: May 21, 2013Assignee: United Microelectronics Corp.Inventors: Tsuo-Wen Lu, I-Ming Lai, Tsung-Yu Hou, Chien-Liang Lin, Wen-Yi Teng, Shao-Wei Wang, Yu-Ren Wang, Chin-Cheng Chien
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Publication number: 20130026464Abstract: A test pattern for measuring semiconductor alloys using X-ray diffraction (XRD) includes a first region to an Nth region defined on a wafer, and a plurality of test structures positioned in the first region and so forth up to in the Nth region. The test structures in the same region have sizes identical to each other and the test structures in different regions have sizes different from each other.Type: ApplicationFiled: July 25, 2011Publication date: January 31, 2013Inventors: Chin-I Liao, Teng-Chun Hsuan, I-Ming Lai, Chin-Cheng Chien
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Publication number: 20130026538Abstract: A semiconductor device having epitaxial structures includes a gate structure positioned on a substrate, epitaxial structures formed in the substrate at two sides of the gate structure, and an undoped cap layer formed on the epitaxial structures. The epitaxial structures include a dopant, a first semiconductor material having a first lattice constant, and a second semiconductor material having a second lattice constant, and the second lattice constant is larger than the first lattice constant. The undoped cap layer also includes the first semiconductor material and the second semiconductor material. The second semiconductor material in the epitaxial structures includes a first concentration, the second semiconductor material in the undoped cap layer includes at least a first concentration, and the second concentration is lower than the first concentration.Type: ApplicationFiled: July 25, 2011Publication date: January 31, 2013Inventors: Chin-I Liao, Teng-Chun Hsuan, I-Ming Lai, Chin-Cheng Chien
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Publication number: 20120270382Abstract: A method of fabricating an epitaxial layer includes providing a substrate. The substrate is etched to form at least a recess within the substrate. A surface treatment is performed on the recess to form a Si—OH containing surface. An in-situ epitaxial process is performed to form an epitaxial layer within the recess, wherein the epitaxial process is performed in a hydrogen-free atmosphere and at a temperature lower than 800° C.Type: ApplicationFiled: April 21, 2011Publication date: October 25, 2012Inventors: Tsuo-Wen Lu, I-Ming Lai, Tsung-Yu Hou, Chien-Liang Lin, Wen-Yi Teng, Shao-Wei Wang, Yu-Ren Wang, Chin-Cheng Chien