Abstract: A TV encoder with a function of adjusting hue for receiving a first and second color mixture signals comprises a first and second multiplexors, a sin-cos generator, a first and second multiplier circuits, and an adder circuits. The first multiplexor alternately outputs the second color mixture signal and its inverted signal. The second multiplexor alternately outputs a first angle signal representative of an angle and a second angle signal representative of the negative value of the angle. The angle is adopted to change the hue. The sin-cos generator outputs a sin and cos signals with a phase angle alternately determined by the angle and its negative value. The first color mixture signal and the sin signal are multiplied through the first multiplier circuit so as to be output as a first product signal. The second color mixture signal and its inverted signal are alternately multiplied by the cos signal through the second multiplier circuit so as to output as a second product signal.

Abstract: A TV encoder with a function of adjusting hue for receiving a first and second color mixture signals comprises a first and second multiplexors, a sin-cos generator, a first and second multiplier circuits, and an adder circuits. The first multiplexor alternately outputs the second color mixture signal and its inverted signal. The second multiplexor alternately outputs a first angle signal representative of an angle and a second angle signal representative of the negative value of the angle. The angle is adopted to change the hue. The sin-cos generator outputs a sin and cos signals with a phase angle alternately determined by the angle and its negative value. The first color mixture signal and the sin signal are multiplied through the first multiplier circuit so as to be output as a first product signal. The second color mixture signal and its inverted signal are alternately multiplied by the cos signal through the second multiplier circuit so as to output as a second product signal.

Abstract: An arithmetic device with low power consumption includes master latches, a dynamic range detection unit, slave latches, an operation unit, and a word-length restoration unit. In the arithmetic device, the master latches latch a plurality of (such as two) input data. The dynamic range detection unit detects the effective dynamic range of these input data. The slave latches latch the values of the effective dynamic-range bits of these input data. The operation unit performs predetermined operations of the bits of these effective dynamic range to obtaing an operation result. Since the operation unit only performs operations of the bits of the effective dynamic range, the circuit corresponding to other bits will not demonstrate switching of power consumption, thereby lowering the overall power consumption. Furthermore, the word-length restoration unit will complement the operation result to its original output length in association with the sign of the operation result, for obtaining the correct operation result.