Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a spacer adjacent to the MTJ, a liner adjacent to the spacer, and a first metal interconnection on the MTJ. Preferably, the first metal interconnection includes protrusions adjacent to two sides of the MTJ and a bottom surface of the protrusions contact the liner directly.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: A semiconductor device includes a magnetic tunneling junction (MTJ) on a substrate, a first spacer on one side of the of the MTJ, a second spacer on another side of the MTJ, a first metal interconnection on the MTJ, and a liner adjacent to the first spacer, the second spacer, and the first metal interconnection. Preferably, each of a top surface of the MTJ and a bottom surface of the first metal interconnection includes a planar surface and two sidewalls of the first metal interconnection are aligned with two sidewalls of the MTJ.

Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.

Abstract: Methods of forming semiconductor devices are provided. The methods include: forming a trench in a substrate, wherein the trench includes a defect protruding from a bottom surface of the trench; forming a flowable material on the substrate to at least partially cover the defect; performing an etching process to reduce the height of the defect; and removing the flowable material.

Abstract: A new method is provided to treat contact holes after hole formation has been completed. A layer of non-conformal dielectric is deposited over the surface in which the contact hole has been formed thereby including the sidewalls and bottom of the contact hole. The non-conformal dielectric will be unevenly deposited on The sidewalls and bottom of the contact hole. This results in a relatively light deposition of non-conformal dielectric along the lower portions of the sidewalls and on the bottom of the contact hole with a heavier coating of non-conformal dielectric being deposited along the upper reaches of the contact hole. The objective of the invention is to prevent the enlargement of the hole diameter during subsequent processing steps. The non-conformal dielectric can be removed from the bottom using a wet etch.

Abstract: A method for forming a via through a silicon oxide layer. There is first provided a substrate. There is then formed over the substrate a patterned silicon nitride layer which defines a contact region beneath the patterned silicon nitride layer. There is then formed over the patterned silicon nitride layer a silicon oxide layer. There is then etched the silicon oxide layer while employing a reactive ion etch (RIE) method employing a first etchant gas composition comprising a fluorocarbon etchant gas to form: (1) an etched silicon oxide layer which exposes the contact region without substantially etching the patterned silicon nitride layer; and (2) a fluorocarbon polymer residue layer formed upon at least one of the etched silicon oxide layer and the patterned silicon nitride layer. Finally, there is stripped from the substrate the fluorocarbon polymer residue layer while employing a downstream plasma etch method employing a second etchant gas composition comprising a fluorocarbon etchant gas and oxygen.

Abstract: A method for simultaneously forming a storage node and a plurality of interconnection in fabricating a semiconductor device on a substrate.

Abstract: A method for etching a metal layer on a substrate with dimensional control is disclosed. First, an anti-reflection layer is formed over the metal layer. A photoresist layer is then formed over the anti-reflection layer. A metal layer pattern is defined by patterning the photoresist layer. An etching process is performed to etch the anti-reflection layer with dimensional loss compared with the metal layer pattern, by using the photoresist layer as a mask. Another etching process is performed to etch the metal layer with dimensional gain compared with the anti-reflection layer, by using the anti-reflection layer as a mask. A metal layer with nearly zero-biased dimension is achieved.

Abstract: A new method of etching AlCu or AlSiCu lines is described. Semiconductor device structures are provided in and on a semiconductor substrate. The semiconductor device structures are covered with an insulating layer. A layer of AlCu or AlSiCu is deposited overlying insulating layer. A silicon nitride or titanium nitride/silicon dioxide layer is deposited overlying the metal layer wherein a hard mask is formed. The hard mask is covered with a layer of photoresist which is exposed to actinic light wherein the hard mask prevents reflection of the actinic light from its surface. The photoresist layer is developed and patterned to form the desired photoresist mask. The hard mask is etched away where it is not covered by the photoresist mask leaving a patterned hard mask. The AlCu or AlSiCu layer and the barrier layer not covered by the patterned hard mask are etched away to form metal lines having an outwardly tapered profile.