Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Abstract: A feeding mechanism for injection-molding machine includes an injection machine frame, which is provided at a middle section with a feeding pipe defining a chamber for receiving heated and softened plastic material therein, such that the received plastic material for injection molding could be pushed forward under an axial pressure from a rear section of the chamber, and in front of the chamber with an injection channel, such that the plastic material in the chamber for injection is injected via a front open end of the injection channel into a mold. The feeding mechanism is characterized in that the feeding pipe is provided at an upper side with a plurality of feeding inlets, so that a plurality of material tanks having differently colored plastic materials stored therein are separately connected thereto for forming an injection-molded product containing different colors through only one injection.

Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Abstract: A packaging container mainly includes a box having an open top and a first flange horizontally outward extended from a periphery of the open top, and a cover having a second flange horizontally outward extended from a periphery of the cover corresponding to the first flange. The first and the second flange are provided at corresponding positions with complementary recess and projection belts that fitly engage with each other to enhance connection of the cover to the box. Outer edges of the first and the second flange are bent downward and upward, respectively, to form a flared peripheral clearance between the cover and the box, allowing the cover to be easily removed from the open top of the box at the flared peripheral clearance.

Abstract: A single-poly two-transistor PMOS memory cell for multiple-time programming applications includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor all formed within a first n-well. A control plate for the floating gate transistor is formed in a second n-well. A single-poly two-transitor PMOS memory cell for one-time programming applications includes a PMOS floating gate transistor having a source formed as a p+ diffusion region in a single n-well. The source is adapted to also serve as control plate for the floating gate transistor.

Abstract: A two-transistor PMOS memory cell includes a PMOS floating gate transistor sharing a drain/source P+ diffusion region with a PMOS select gate transistor. The shared drain/source diffusion region acts as a drain for the floating gate transistor and as a source to the select gate transistor. The shared drain/source P+ diffusion region is formed in an N? well. Underlying the drain/source P+ diffusion region is a N implant having the same lateral extent of the drain/source P+ diffusion region to provide a lower programming voltage for the floating gate transistor and improved punch-through resistance for the select gate transistor.

Abstract: A DRAM having a guard ring comprises a semiconductor substrate having a memory array area and a guard ring area; a first trench disposed on said memory array area; a second trench disposed on said guard ring area; a first doped strap disposed on the upper surface of said semiconductor substrate around said first trench; a second doped strap disposed on the upper surface of said semiconductor substrate around said second trench. Furthermore, the DRAM comprises a first doped plate disposed on said semiconductor substrate around the bottom of said first trench, and is separated from said first doped strap by a predetermined distance; and a second doped plate disposed on said semiconductor substrate around the bottom of said second trench, and is connected to said second doped strap.

Abstract: A DRAM having a guard ring comprises a semiconductor substrate having a memory array area and a guard ring area; a first trench disposed on said memory array area; a second trench disposed on said guard ring area; a first doped strap disposed on the upper surface of said semiconductor substrate around said first trench; a second doped strap disposed on the upper surface of said semiconductor substrate around said second trench. Furthermore, the DRAM comprises a first doped plate disposed on said semiconductor substrate around the bottom of said first trench, and is separated from said first doped strap by a predetermined distance; and a second doped plate disposed on said semiconductor substrate around the bottom of said second trench, and is connected to said second doped strap.