Abstract: A hanging structure applicable to an unmanned aerial vehicle includes a hook-shaped body and at least one hook claw. The hook-shaped body has a bottom, at least one pivoting end, and an abutting portion. A hook opening is provided between the at least one pivoting end and the abutting portion and is opposite to the bottom. In addition, the at least one hook claw has a pivoting portion, and a first claw portion and a second claw portion that extend from the pivoting portion, respectively. The pivoting portion is pivoted to the at least one pivoting end. The second claw portion is heavier than the first claw portion. When the hanging structure is in a hanging state, a first end of the first claw portion abuts against the abutting portion, and the hook opening is closed. An unmanned aerial vehicle hanging system including the above hanging structure is further provided.

Abstract: The present disclosure provides a circuit board with an embedded chip, which includes a dielectric layer, a first circuit layer, a chip, a conductive connector, and an insulating protection layer. The first circuit layer includes at least one first trace in the dielectric layer. The chip is in the dielectric layer and adjacent to the first trace, where the chip includes a plurality of chip pads at an upper surface of the chip. The conductive connector is on the upper surface of the chip and on the first circuit layer, where a lower surface of the conductive connector contacts at least one chip pad of the chip pads and an upper surface of the first trace. The insulating protection layer is on the chip, the first circuit layer, and the conductive connector, where the insulating protection layer contacts the upper surface of the chip.

Abstract: A data processing method includes reading a memory device in response to a read command to respectively read multiple portions of predetermined data; respectively writing the portions in a buffer memory to complete data transfers of the portions of the predetermined data; sequentially providing access information corresponding to each portion of the predetermined data in response to completion of the data transfer of the corresponding portion; obtaining the access information of the predetermined data and accordingly generating multiple descriptors in chronological order of obtaining the access information; receiving and buffering the descriptors in a descriptor pool; sequentially selecting a latest descriptor from the descriptor pool according to a tag value and providing the latest descriptor to a direct memory access engine; and reading the buffer memory according to the latest descriptor to obtain at least a portion of the predetermined data by the direct memory access engine.

Abstract: A method for performing access management of a memory device in predetermined communications architecture with aid of flexible delay time control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit within the memory controller to dynamically set a delay parameter regarding transmission from the memory device to a host device, for preventing sleeping in delay time(s) corresponding to the delay parameter; utilizing a physical layer (PHY) circuit of the transmission interface circuit to transmit first data from the memory device to the host device, wherein a first delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed; and utilizing the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.

Abstract: A method for performing access management of a memory device in predetermined communications architecture with aid of flexible delay time control and associated apparatus are provided. The method may include: utilizing at least one upper layer controller of a transmission interface circuit within the memory controller to dynamically set a delay parameter regarding transmission from the memory device to a host device, for preventing sleeping in delay time(s) corresponding to the delay parameter; utilizing a physical layer (PHY) circuit of the transmission interface circuit to transmit first data from the memory device to the host device, wherein a first delay time starts from a first time point at which transmitting the first data from the memory device to the host device is completed; and utilizing the PHY circuit to start transmitting second data from the memory device to the host device in the first delay time without restarting from sleeping.

Abstract: An electronic device comprises a clock request pad, a multiplexer and a control circuit. The clock request pad is arranged to refer to a first control signal to operate under a low voltage level or a high voltage level, to indicate whether the electronic device needs a clock signal generated from a clock generation circuit external to the electronic device. Said multiplexer is arranged to refer to a second control signal to output one of a voltage level of the clock request pad and a predetermined voltage level to function as a multiplexer output signal. The control circuit is coupled to said multiplexer, and refers to said multiplexer output signal to determine whether to control the electronic device to operate in a power-saving mode.

Abstract: An electronic device comprises a clock request pad, a multiplexer and a control circuit. The clock request pad is arranged to refer to a first control signal to operate under a low voltage level or a high voltage level, to indicate whether the electronic device needs a clock signal generated from a clock generation circuit external to the electronic device. Said multiplexer is arranged to refer to a second control signal to output one of a voltage level of the clock request pad and a predetermined voltage level to function as a multiplexer output signal. The control circuit is coupled to said multiplexer, and refers to said multiplexer output signal to determine whether to control the electronic device to operate in a power-saving mode.

Abstract: A circuit for recognizing a beginning and a data rate of data includes at least two data rate detecting units and a post processing unit. The at least two data rate detecting units are used for comparing at least two alignment patterns corresponding to different data rates with data simultaneously to recognize a data rate of the data. The post processing unit is coupled to the at least two data rate detecting units for recognizing a beginning of the data according to an alignment pattern corresponding to the data when the data rate of the data is recognized.

Abstract: A circuit for recognizing a beginning and a data rate of data includes at least two data rate detecting units and a post processing unit . The at least two data rate detecting units are used for comparing at least two alignment patterns corresponding to different data rates with data simultaneously to recognize a data rate of the data. The post processing unit is coupled to the at least two data rate detecting units for recognizing a beginning of the data according to an alignment pattern corresponding to the data when the data rate of the data is recognized.