Abstract: A wafer holding structure for wafer backside processing, in which the wafer comprises a SiC substrate and a semiconductor device layer. The SiC substrate has a back surface and a front surface, and the semiconductor device layer has a first surface and a second surface. The semiconductor device layer is disposed on the SiC substrate with its first surface in contact with the front surface of the SiC substrate. The wafer holding structure comprises a wafer carrier and an adhesive coating. The wafer carrier is made of n-type conductive SiC, and has a thermal expansion coefficient that is well matched to the SiC substrate. The wafer carrier is mounted to the second surface of the semiconductor device layer and the adhesive coating is coated between the wafer carrier and the second surface of the semiconductor device layer.

Abstract: A method for forming a through wafer via hole in a semiconductor device, wherein the semiconductor device comprises a wafer having a SiC substrate with a front side and a backside, a GaN-based layer formed on the front side of the SiC substrate, and a mask structure formed on the backside of the SiC substrate defining an etching area. The etching area is first descummed A through substrate via hole is formed by etching the etching area through the SiC substrate. The mask structure is removed and the inner surface of the through substrate via hole is cleaned. The inner surface of the through substrate via hole is then descummed A through wafer via hole is formed by etching through the GaN layer in the through substrate via hole. And lastly the inner surface of the through wafer via hole is cleaned.

Abstract: A wafer edge protector is used in an inductively coupled plasma reactive ion etching instrument for the manufacturing of GaN semiconductor devices and circuits. The wafer edge protector comprises a ring clamp, which has a first inner diameter and a second inner diameter, and the ring clamp covers the edges of a wafer and a wafer carrier to clamp the wafer and the wafer carrier and to prevent damage on the edges of the wafer and the wafer carrier during the etching process.