Patents by Inventor I-Ting Lin
I-Ting Lin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240151930Abstract: The present invention relates to an aperture unit having an optical axis. The aperture unit includes a fixed portion, a guiding element, a first blade and a driving assembly. The guiding element is movably connected to the fixed portion, and the first blade is movably connected to the guiding element and the fixed portion. The driving assembly is disposed on the guiding element for driving the guiding element to move relative to the fixed portion in a first moving dimension. When the guiding element moves relative to the fixed portion in the first moving dimension, the first blade is driven by the guiding element to move relative to the fixed portion in a second moving dimension, and the first moving dimension and the second moving dimension are different.Type: ApplicationFiled: January 12, 2024Publication date: May 9, 2024Inventors: Kuo-Chun KAO, Meng-Ting LIN, I-Mei HUANG, Sin-Jhong SONG
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Publication number: 20240144585Abstract: A computing device obtains an image depicting a face of a user. The computing device identifies facial features in the image and extracts characteristics of the facial features in the image. The computing device generates a two-dimensional (2D) face chart based on the facial feature characteristics. The computing device predicts a skin tone of the user's face depicted in the image of the user and changes color in a color map of a predefined three-dimensional (3D) model based on the predicted skin tone. The computing device selects a predefined environment map based on characteristics in the image depicting the face of the user and generates a target face image based on the predefined 3D model.Type: ApplicationFiled: October 26, 2023Publication date: May 2, 2024Inventors: I-Ting SHEN, Yi-Wei LIN, Pei-Wen HUANG
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Patent number: 11948896Abstract: A package structure is provided. The package structure includes a through substrate via structure, a first stacked die package structure, an underfill layer, and a package layer. The through substrate via structure is formed over a substrate. The first stacked die package structure is over the through substrate via structure, wherein the first stacked die package structure comprises a plurality of memory dies. The underfill layer is over the first stacked die package structure. the package layer is over the underfill layer, wherein the package layer has a protruding portion that extends below a top surface of the through substrate via structure.Type: GrantFiled: July 26, 2022Date of Patent: April 2, 2024Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Tsung-Fu Tsai, Kung-Chen Yeh, I-Ting Huang, Shih-Ting Lin, Szu-Wei Lu
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Publication number: 20230387092Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: August 8, 2023Publication date: November 30, 2023Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Patent number: 11721678Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: GrantFiled: May 25, 2021Date of Patent: August 8, 2023Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
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Publication number: 20210280565Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: May 25, 2021Publication date: September 9, 2021Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Patent number: 11018120Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: GrantFiled: June 6, 2019Date of Patent: May 25, 2021Assignee: ADVANCED SEMICONDUCTOR ENGINEERING, INC.Inventors: Chien-Mei Huang, Shih-Yu Wang, I-Ting Lin, Wen Hung Huang, Yuh-Shan Su, Chih-Cheng Lee, Hsing Kuo Tien
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Publication number: 20200388600Abstract: A semiconductor device package includes a first conductive structure, a stress buffering layer and a second conductive structure. The first conductive structure includes a substrate, at least one first electronic component embedded in the substrate, and a first circuit layer disposed on the substrate and electrically connected to the first electronic component. The first circuit layer includes a conductive wiring pattern. The stress buffering layer is disposed on the substrate. The conductive wiring pattern of the first circuit layer extends through the stress buffering layer. The second conductive structure is disposed on the stress buffering layer and the first circuit layer.Type: ApplicationFiled: June 6, 2019Publication date: December 10, 2020Applicant: Advanced Semiconductor Engineering, Inc.Inventors: Chien-Mei HUANG, Shih-Yu WANG, I-Ting LIN, Wen Hung HUANG, Yuh-Shan SU, Chih-Cheng LEE, Hsing Kuo TIEN
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Patent number: 10424593Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.Type: GrantFiled: January 9, 2018Date of Patent: September 24, 2019Assignee: MACRONIX International Co., Ltd.Inventors: I-Ting Lin, Yuan-Chieh Chiu, Hong-Ji Lee
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Publication number: 20190214402Abstract: A three-dimensional non-volatile memory and a method of manufacturing the same are provided. The three-dimensional non-volatile memory includes a substrate, a charge storage structure, a stacked structure and a channel layer. The charge storage structure is disposed on the substrate. The stacked structure is disposed at a side of the charge storage structure and includes insulating layers, gates, a buffer layer and a barrier layer. The insulating layers and the gates are alternately stacked. The buffer layer is disposed between each of the gates and the charge storage structure and on the surfaces of the insulating layers. The barrier layer is disposed between each of the gates and the buffer layer. An end of the gate is convex with respect to an end of the barrier layer in a direction away from the channel layer.Type: ApplicationFiled: January 9, 2018Publication date: July 11, 2019Applicant: MACRONIX International Co., Ltd.Inventors: I-Ting Lin, Yuan-Chieh Chiu, Hong-Ji Lee
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Patent number: 10050051Abstract: A memory device includes memory includes a multi-layers stack includes a plurality of insulating layers and a plurality conductive layers alternatively stacked on a semiconductor device, a plurality of memory cells formed on the conductive layers, a contact plug passing through the insulating layers and the conductive layers, and a dielectric layer including a plurality of extending parts each of which is inserted between each adjacent two ones of the insulating layers to isolate the conductive layer from the contact plug, wherein any one of the extending parts that has a shorter distance departed from the semiconductor substrate has a size substantially greater than a size of the others that has a longer distance departed from the semiconductor substrate.Type: GrantFiled: March 22, 2017Date of Patent: August 14, 2018Assignee: MACRONIX INTERNATIONAL CO., LTD.Inventors: Ting-Feng Liao, I-Ting Lin