Patents by Inventor I Tseng

I Tseng has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12266852
    Abstract: An electronic device is provided. The electronic device includes a first substrate, an insulating layer, a first conductive layer and a second conductive layer. The insulating layer is overlapped with the first substrate. The second conductive layer contacts with the first conductive layer. The first conductive layer and the second conductive layer are disposed between the first substrate and the insulating layer. The second conductive layer is disposed between the first conductive layer and the insulating layer. Moreover, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the insulating layer.
    Type: Grant
    Filed: January 2, 2024
    Date of Patent: April 1, 2025
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Ping Tseng, Ker-Yih Kao, Chia-Chi Ho, Ming-Yen Weng, Hung-I Tseng, Shu-Ling Wu, Huei-Ying Chen
  • Patent number: 12191197
    Abstract: A manufacturing method of a package structure of an electronic device, including the following steps, is provided. A first seed layer is formed on a carrier plate. A first metal layer is formed on the first seed layer. A first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. A first plasma treatment is performed on the first insulating layer and the exposed portion of the first metal layer. After performing the first plasma treatment, the carrier plate formed with the first seed layer, the first metal layer, and the first insulating layer is placed in a microenvironment controlling box. After taking the carrier plate out of the microenvironment controlling box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer.
    Type: Grant
    Filed: May 18, 2022
    Date of Patent: January 7, 2025
    Assignee: Innolux Corporation
    Inventors: Ching-Wei Chen, Yu-Jen Chang, Tzu-Yen Chiu, Hung-I Tseng, Chuan-Ming Yeh, Heng-Shen Yeh
  • Patent number: 12026075
    Abstract: A power supply health check system for checking a health state of an under-test power supply is provided. The under-test power supply supplies power to a main board which has a voltage signal during operation. The health check system includes a detecting module, a deep learning model, and a processing unit. The detecting module is electrically connected to the main board to detect the voltage signal and convert the voltage signal into a digital signal. The deep learning model is established by using frequency-domain voltage data of a plurality of healthy power. The processing unit is configured to: collect the digital signal and store the digital signal as under-test time-domain voltage data; convert the under-test time-domain voltage data into under-test frequency-domain voltage data; and calculate, based on the under-test frequency-domain voltage data and the deep learning model, a health indicator for determining the health state of the under-test power supply.
    Type: Grant
    Filed: December 1, 2022
    Date of Patent: July 2, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Cheng-Wei Gu, Shu-Chiao Liao, Ming-Hung Chung, Yao-Hsun Huang, Yuan-I Tseng, Hung-Ju Lin
  • Patent number: 11990111
    Abstract: A noise measuring device is provided. The noise measuring device includes a soundproof box, a sound receiving device, a holding device, and a driving device. The sound receiving device is disposed in the soundproof box. The holding device is disposed in the soundproof box and configured to hold a testing object. The driving device is connected with the soundproof box and configure to drive the soundproof box to rotate.
    Type: Grant
    Filed: August 16, 2021
    Date of Patent: May 21, 2024
    Assignee: ASUSTEK COMPUTER INC.
    Inventors: Sheng-Pin Su, Yuan-I Tseng, Che-Hung Lai, Chien-Yi Wang, Chuan-Te Chang
  • Publication number: 20240162602
    Abstract: An electronic device is provided. The electronic device includes a first substrate, an insulating layer, a first conductive layer and a second conductive layer. The insulating layer is overlapped with the first substrate. The second conductive layer contacts with the first conductive layer. The first conductive layer and the second conductive layer are disposed between the first substrate and the insulating layer. The second conductive layer is disposed between the first conductive layer and the insulating layer. Moreover, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the insulating layer.
    Type: Application
    Filed: January 2, 2024
    Publication date: May 16, 2024
    Inventors: Chia-Ping TSENG, Ker-Yih KAO, Chia-Chi HO, Ming-Yen WENG, Hung-I TSENG, Shu-Ling WU, Huei-Ying CHEN
  • Patent number: 11901618
    Abstract: An electronic device is provided. The electronic device includes a first substrate, a multilayer structure, and a passivation layer. The multilayer structure is disposed on the first substrate. The multilayer structure includes a first conductive layer and a second conductive layer disposed on the first conductive layer. The passivation layer is disposed on the second conductive layer. In addition, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the passivation layer.
    Type: Grant
    Filed: September 6, 2022
    Date of Patent: February 13, 2024
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Ping Tseng, Ker-Yih Kao, Chia-Chi Ho, Ming-Yen Weng, Hung-I Tseng, Shu-Ling Wu, Huei-Ying Chen
  • Publication number: 20230350772
    Abstract: A power supply health check system for checking a health state of an under-test power supply is provided. The under-test power supply supplies power to a main board which has a voltage signal during operation. The health check system includes a detecting module, a deep learning model, and a processing unit. The detecting module is electrically connected to the main board to detect the voltage signal and convert the voltage signal into a digital signal. The deep learning model is established by using frequency-domain voltage data of a plurality of healthy power. The processing unit is configured to: collect the digital signal and store the digital signal as under-test time-domain voltage data; convert the under-test time-domain voltage data into under-test frequency-domain voltage data; and calculate, based on the under-test frequency-domain voltage data and the deep learning model, a health indicator for determining the health state of the under-test power supply.
    Type: Application
    Filed: December 1, 2022
    Publication date: November 2, 2023
    Inventors: Cheng-Wei GU, Shu-Chiao LIAO, Ming-Hung CHUNG, Yao-Hsun HUANG, Yuan-I TSENG, Hung-Ju LIN
  • Publication number: 20230341464
    Abstract: A signal abnormality detection system and a method thereof are provided. The signal abnormality detection system includes a signal sensor and a computing device. The signal sensor generates a sample signal to be tested through sensing. The computing device is signal-connected to the signal sensor to receive the sample signal to be tested, perform a correction on the sample signal to be tested, and perform a time-frequency transform on a one-dimensional signal generated after the correction to generate a two-dimensional time-frequency signal. The computing device reconstructs the two-dimensional time-frequency signal by using an abnormality detection model to calculate a reconstructed difference value. The computing device performs comparison to determine whether the reconstructed difference value is greater than a detection threshold to determine whether the sample signal to be tested is an abnormal sample.
    Type: Application
    Filed: November 3, 2022
    Publication date: October 26, 2023
    Inventors: Hung-Ju Lin, Yuan-I Tseng, Cheng-Wei Gu, Shu-Chiao Liao
  • Publication number: 20230238278
    Abstract: A manufacturing method of a package structure of an electronic device, including the following steps, is provided. A first seed layer is formed on a carrier plate. A first metal layer is formed on the first seed layer. A first insulating layer is formed on the first metal layer, wherein the first insulating layer exposes a portion of the first metal layer. A first plasma treatment is performed on the first insulating layer and the exposed portion of the first metal layer. After performing the first plasma treatment, the carrier plate formed with the first seed layer, the first metal layer, and the first insulating layer is placed in a microenvironment controlling box. After taking the carrier plate out of the microenvironment controlling box, a second seed layer is formed on the first insulating layer and the exposed portion of the first metal layer.
    Type: Application
    Filed: May 18, 2022
    Publication date: July 27, 2023
    Applicant: Innolux Corporation
    Inventors: Ching-Wei Chen, Yu-Jen Chang, Tzu-Yen Chiu, Hung-I Tseng, Chuan-Ming Yeh, Heng-Shen Yeh
  • Publication number: 20230178447
    Abstract: A method for manufacturing a composite layer circuit structure of an electronic device is provided. First, a first conductive layer is formed on a carrier plate. Next, a first photoresist layer is formed on the first conductive layer. The first photoresist layer includes multiple first openings exposing part of the first conductive layer. Next, a first electroplating layer is formed in the first openings. Then, the first photoresist layer is removed. Then, a first insulating layer is formed on the first conductive layer. The first insulating layer includes multiple second openings exposing part of the first electroplating layer. In the above, at least one heat treatment process is performed on the first electroplating layer before the first insulating layer is formed on the first conductive layer. A temperature when performing at least one heat treatment process is higher than or equal to 40° C. and lower than or equal to 300° C.
    Type: Application
    Filed: May 23, 2022
    Publication date: June 8, 2023
    Applicant: Innolux Corporation
    Inventors: Yu-Jen Chang, Ching-Wei Chen, Tzu-Yen Chiu, Hung-I Tseng, Chun-Chin Fan
  • Publication number: 20230089751
    Abstract: An electronic device includes a first metal layer, a first insulating layer, a second metal layer and a second insulating layer. The first insulating layer is disposed on the first metal layer, the second metal layer is disposed on the first insulating layer, and the second insulating layer is disposed between the second metal layer and the first insulating layer. The second metal layer is electrically connected to the first metal layer through a first opening of the first insulating layer and a second opening of the second insulating layer.
    Type: Application
    Filed: May 3, 2022
    Publication date: March 23, 2023
    Applicant: InnoLux Corporation
    Inventors: Ker-Yih KAO, Hung-I TSENG
  • Publication number: 20230006342
    Abstract: An electronic device is provided. The electronic device includes a first substrate, a multilayer structure, and a passivation layer. The multilayer structure is disposed on the first substrate. The multilayer structure includes a first conductive layer and a second conductive layer disposed on the first conductive layer. The passivation layer is disposed on the second conductive layer. In addition, a thermal expansion coefficient of the second conductive layer is between a thermal expansion coefficient of the first conductive layer and a thermal expansion coefficient of the passivation layer.
    Type: Application
    Filed: September 6, 2022
    Publication date: January 5, 2023
    Inventors: Chia-Ping TSENG, Ker-Yih KAO, Chia-Chi HO, Ming-Yen WENG, Hung-I TSENG, Shu-Ling WU, Huei-Ying CHEN
  • Patent number: 11474136
    Abstract: A method for examining differential pair transmission lines, performed by a processor, comprising: capturing a plurality of first insertion losses of a first signal line within a frequency range and a plurality of second insertion losses of a second signal line within the frequency range, wherein the first signal line and the second signal line are configured to transmit a pair of differential signals; calculating a plurality of maximum error ratios between the first insertion losses and the second insertion losses within the frequency range; determining whether any one of the maximum error ratios is greater than or equal to an upper threshold; outputting a warning signal when the processor determines one of the maximum error ratios is greater than or equal to the upper threshold; and ending the method when the processor determines each one of the maximum error ratios is smaller than the upper threshold.
    Type: Grant
    Filed: December 13, 2019
    Date of Patent: October 18, 2022
    Assignees: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Chun I Tseng, Yen-Hao Chen
  • Patent number: 11469491
    Abstract: An antenna device is provided. The antenna device includes a first substrate, a multilayer electrode, a second substrate, and a liquid-crystal layer. The multilayer electrode is disposed on the first substrate, and the multilayer electrode includes a first conductive layer, a second conductive layer, and a third conductive layer. The second conductive layer is disposed on the first conductive layer. The third conductive layer is disposed on the second conductive layer. The liquid-crystal layer is disposed between the first substrate and the second substrate. In addition, the third conductive layer includes a first portion that extends beyond the second conductive layer.
    Type: Grant
    Filed: January 2, 2020
    Date of Patent: October 11, 2022
    Assignee: INNOLUX CORPORATION
    Inventors: Chia-Ping Tseng, Ker-Yih Kao, Chia-Chi Ho, Ming-Yen Weng, Hung-I Tseng, Shu-Ling Wu, Huei-Ying Chen
  • Publication number: 20220208559
    Abstract: Chip manufacturing, including: assembling at least two chips on a layer; and applying mold compound on the at least two chips to the sides and bottom including flowing around interconnects, thereby leaving the top of each of the at least two chips exposed.
    Type: Application
    Filed: December 30, 2020
    Publication date: June 30, 2022
    Inventors: Ai-Tee Ang, I-Tseng Lee
  • Publication number: 20220093071
    Abstract: A noise measuring device is provided. The noise measuring device includes a soundproof box, a sound receiving device, a holding device, and a driving device. The sound receiving device is disposed in the soundproof box. The holding device is disposed in the soundproof box and configured to hold a testing object. The driving device is connected with the soundproof box and configure to drive the soundproof box to rotate.
    Type: Application
    Filed: August 16, 2021
    Publication date: March 24, 2022
    Inventors: Sheng-Pin SU, Yuan-I TSENG, Che-Hung LAI, Chien-Yi WANG, Chuan-Te CHANG
  • Publication number: 20210390404
    Abstract: The disclosure provides a signal detection method. The signal detection method includes: collecting initial data; pre-processing the initial data to obtain an original signal; reconstructing the original signal by using an optimized deep learning model, to generate a reconstructed signal; and comparing the original signal with the reconstructed signal, to determine whether there is an abnormality in the original signal. The disclosure further provides an electronic device using the signal detection method.
    Type: Application
    Filed: June 3, 2021
    Publication date: December 16, 2021
    Inventors: Yuan-I TSENG, Po-Yin LAI, Shu-Chiao LIAO
  • Patent number: 10957640
    Abstract: A semiconductor structure includes a conductive structure, a dielectric layer, and a plurality of conductive features. The dielectric layer is present on the conductive structure. The dielectric layer has a plurality of through holes therein, and at least one of the through holes exposes the conductive structure. The conductive features are respectively present in the through holes. At least one of the conductive features has a bottom surface and at least one sidewall. The bottom surface and the sidewall of the conductive feature intersect to form an interior angle. The interior angles of adjacent two of the conductive features have a difference less than or substantially equal to about 3 degrees.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: March 23, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Yu-Hung Lin, Chun-Hsien Huang, I-Tseng Chen
  • Publication number: 20210072299
    Abstract: A method for examining differential pair transmission lines, performed by a processor, comprising: capturing a plurality of first insertion losses of a first signal line within a frequency range and a plurality of second insertion losses of a second signal line within the frequency range, wherein the first signal line and the second signal line are configured to transmit a pair of differential signals; calculating a plurality of maximum error ratios between the first insertion losses and the second insertion losses within the frequency range; determining whether any one of the maximum error ratios is greater than or equal to an upper threshold; outputting a warning signal when the processor determines one of the maximum error ratios is greater than or equal to the upper threshold; and ending the method when the processor determines each one of the maximum error ratios is smaller than the upper threshold.
    Type: Application
    Filed: December 13, 2019
    Publication date: March 11, 2021
    Applicants: INVENTEC (PUDONG) TECHNOLOGY CORPORATION, INVENTEC CORPORATION
    Inventors: Chun I TSENG, Yen-Hao CHEN
  • Publication number: 20200251812
    Abstract: An antenna device is provided. The antenna device includes a first substrate, a multilayer electrode, a second substrate, and a liquid-crystal layer. The multilayer electrode is disposed on the first substrate, and the multilayer electrode includes a first conductive layer, a second conductive layer, and a third conductive layer. The second conductive layer is disposed on the first conductive layer. The third conductive layer is disposed on the second conductive layer. The liquid-crystal layer is disposed between the first substrate and the second substrate. In addition, the third conductive layer includes a first portion that extends beyond the second conductive layer.
    Type: Application
    Filed: January 2, 2020
    Publication date: August 6, 2020
    Inventors: Chia-Ping TSENG, Ker-Yih KAO, Chia-Chi HO, Ming-Yen WENG, Hung-I TSENG, Shu-Ling WU, Huei-Ying CHEN