Patents by Inventor I-Tseng Lee

I-Tseng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180102296
    Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
    Type: Application
    Filed: December 11, 2017
    Publication date: April 12, 2018
    Applicant: Advanced Micro Device (Shanghai) Co., Ltd.
    Inventors: I-Tseng LEE, Yu-Ling HSIEH
  • Patent number: 9870969
    Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
    Type: Grant
    Filed: February 28, 2014
    Date of Patent: January 16, 2018
    Assignee: ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.
    Inventors: I-Tseng Lee, Yu-Ling Hsieh
  • Patent number: 9214438
    Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.
    Type: Grant
    Filed: February 27, 2015
    Date of Patent: December 15, 2015
    Assignee: Advanced Micro Devices (Shanghai) Co., Ltd.
    Inventors: I-Tseng Lee, Yi Hsiu Liu
  • Publication number: 20150171043
    Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.
    Type: Application
    Filed: February 27, 2015
    Publication date: June 18, 2015
    Inventors: I-Tseng Lee, Yi Hsiu Liu
  • Patent number: 8994191
    Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.
    Type: Grant
    Filed: January 21, 2014
    Date of Patent: March 31, 2015
    Assignee: Advanced Micro Devices (Shanghai) Co. Ltd.
    Inventors: I-Tseng Lee, Yi Hsiu Liu
  • Publication number: 20140306338
    Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.
    Type: Application
    Filed: January 21, 2014
    Publication date: October 16, 2014
    Inventors: I-Tseng Lee, Yi Hsiu Liu
  • Publication number: 20140246223
    Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.
    Type: Application
    Filed: February 28, 2014
    Publication date: September 4, 2014
    Applicant: Advanced Micro Devices (Shanghai) Co., Ltd.
    Inventors: I-Tseng Lee, Yu-Ling Hsieh
  • Publication number: 20120326299
    Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a first polymer film to a side of a semiconductor chip and forming a first underbump metallization structure with at least a portion on the first polymer film. A second polymer film is applied on the first polymer film with an opening exposing a portion of the first underbump metallization structure.
    Type: Application
    Filed: June 24, 2011
    Publication date: December 27, 2012
    Inventors: Roden R. Topacio, I-Tseng Lee
  • Publication number: 20110299259
    Abstract: Various circuit board interconnect conductor structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is disclosed that includes forming a conductor post on a side of a circuit board. The conductor post includes an end projecting away from the side of the circuit board. A solder mask is applied to the side of the circuit board to cover the conductor post. A thickness of the solder mask is reduced so that a portion of the conductor post projects beyond the solder mask.
    Type: Application
    Filed: June 4, 2010
    Publication date: December 8, 2011
    Inventors: Yu-Ling Hsieh, I-Tseng Lee, Yi-Hsiu Liu, Jen-Yi Tsai, Cheng-hua Fan
  • Publication number: 20110278054
    Abstract: Various circuit board conductor structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided. The method includes forming a first conductor pad on a circuit board. The first conductor pad includes a first notch and is adapted to couple to a first solder portion.
    Type: Application
    Filed: May 14, 2010
    Publication date: November 17, 2011
    Inventors: I-Tseng Lee, Yi-Hsiu Liu, Jen-Yi Tsai
  • Patent number: 7248477
    Abstract: A fan-shaped dissipating device, which is assembled on a chip of an erect PCB, has a conductive board, and a plurality of fins. The fins are respectively connected on an outside surface of the conductive board. Each of the fins has a top end and a bottom end. An interval between each two adjacent top ends of the fins is larger that between each two adjacent bottom ends of the fins. The fins are arranged in a radiating manner toward two sides from the bottom ends to the upper ends, therefore reducing the density of the accumulated air between the top ends of the fins because of rising hot air, and providing a better dissipating effect.
    Type: Grant
    Filed: October 6, 2004
    Date of Patent: July 24, 2007
    Assignee: Via Technologies, Inc.
    Inventors: I-Tseng Lee, Shih-Chang Ku
  • Patent number: 7143509
    Abstract: A circuit board essentially comprises a first laminated structure, at least a first plated through hole, at least a second laminated structure, a middle dielectric layer and at least a second plated through hole is disclosed. The first laminated structure has at least three first circuit layers and at last two first dielectric layers. The first circuit layers and the first dielectric layers are alternately laminated and any two adjacent first circuit layers have a first dielectric layer disposed between them. The first plated through hole passes through the first laminated layer. The second laminated structure is laminated over the first laminated structure. The middle dielectric layer is disposed between the first laminated structure and the second laminated structure. The second plated through hole passes through the first laminated structure, the middle dielectric layer and the second laminated structure.
    Type: Grant
    Filed: May 31, 2005
    Date of Patent: December 5, 2006
    Assignee: VIA Technologies, Inc.
    Inventor: I-Tseng Lee
  • Patent number: 7078794
    Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, a plurality of conductive wires and an insulating material is provided. The substrate has a first surface and a corresponding second surface. The substrate has a slot that penetrates the substrate. The chip is attached to the first surface of the substrate in a position that covers the slot. The conductive wires pass through the slot such that one end of each conductive wire is attached to a contact point on the chip while the other end of the conductive wire is attached to a contact point on the second surface of the substrate. The insulating material fills the space between the chip and the substrate and the slot so that the conductive wires and the bumps are enclosed.
    Type: Grant
    Filed: June 20, 2003
    Date of Patent: July 18, 2006
    Assignee: VIA Technologies, Inc.
    Inventor: I Tseng Lee
  • Publication number: 20060112548
    Abstract: A circuit board essentially comprises a first laminated structure, at least a first plated through hole, at least a second laminated structure, a middle dielectric layer and at least a second plated through hole is disclosed. The first laminated structure has at least three first circuit layers and at last two first dielectric layers. The first circuit layers and the first dielectric layers are alternately laminated and any two adjacent first circuit layers have a first dielectric layer disposed between them. The first plated through hole passes through the first laminated layer. The second laminated structure is laminated over the first laminated structure. The middle dielectric layer is disposed between the first laminated structure and the second laminated structure. The second plated through hole passes through the first laminated structure, the middle dielectric layer and the second laminated structure.
    Type: Application
    Filed: May 31, 2005
    Publication date: June 1, 2006
    Inventor: I-Tseng Lee
  • Publication number: 20050237718
    Abstract: A fan-shaped dissipating device, which is assembled on a chip of an erect PCB, has a conductive board, and a plurality of fins. The fins are respectively connected on an outside surface of the conductive board. Each of the fins has a top end and a bottom end. An interval between each two adjacent top ends of the fins is larger that between each two adjacent bottom ends of the fins. The fins are arranged in a radiating manner toward two sides from the bottom ends to the upper ends, therefore reducing the density of the accumulated air between the top ends of the fins because of rising hot air, and providing a better dissipating effect.
    Type: Application
    Filed: October 6, 2004
    Publication date: October 27, 2005
    Inventors: I-Tseng Lee, Shih-Chang Ku
  • Patent number: 6946601
    Abstract: An electronic package with a passive component includes a circuit carrier, at least a passive component and an anisotropic conductive layer. The circuit carrier has at least a passive-component-pad set including multiple pads. The passive component has multiple electrodes placed over the corresponding pads of the passive-component-pad set. The anisotropic conductive layer is deposited between the electrodes and the pads.
    Type: Grant
    Filed: September 30, 2004
    Date of Patent: September 20, 2005
    Assignee: VIA Technologies Inc.
    Inventors: I-Tseng Lee, Jen-Te Tseng
  • Patent number: 6919628
    Abstract: A stack chip package structure is provided. One principal feature of the structure is the formation of a few peripheral surfaces (e.g. ladder or lead-angle surfaces) at the bottom peripheral sections of a stack structure. When the stack structure is attached to a surface of a die through an adhesive layer, the thickness of the adhesive layer under a peripheral section of the stack structure is greater than a central region. Therefore, as the chip package is subjected to a thermal stress test, the adhesive layer under the peripheral sections of the stack structure is able to provide some buffering against thermal stress so that the stress concentration around the stack structure is reduced. Consequently, damages of the die surface due to stress are prevented and the average working life of the chip package is extended.
    Type: Grant
    Filed: July 18, 2003
    Date of Patent: July 19, 2005
    Assignee: Via Technologies, Inc.
    Inventors: I-Tseng Lee, Hsueh Kuo Liao, Jen-Te Tseng
  • Publication number: 20040164389
    Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, a plurality of conductive wires and an insulating material is provided. The substrate has a first surface and a corresponding second surface. The substrate has a slot that penetrates the substrate. The chip is attached to the first surface of the substrate in a position that covers the slot. The conductive wires pass through the slot such that one end of each conductive wire is attached to a contact point on the chip while the other end of the conductive wire is attached to a contact point on the second surface of the substrate. The insulating material fills the space between the chip and the substrate and the slot so that the conductive wires and the bumps are enclosed.
    Type: Application
    Filed: June 20, 2003
    Publication date: August 26, 2004
    Inventor: I TSENG LEE
  • Publication number: 20040140546
    Abstract: A stack chip package structure is provided. One principal feature of the structure is the formation of a few peripheral surfaces (e.g. ladder or lead-angle surfaces) at the bottom peripheral sections of a stack structure. When the stack structure is attached to a surface of a die through an adhesive layer, the thickness of the adhesive layer under a peripheral section of the stack structure is greater than a central region. Therefore, as the chip package is subjected to a thermal stress test, the adhesive layer under the peripheral sections of the stack structure is able to provide some buffering against thermal stress so that the stress concentration around the stack structure is reduced. Consequently, damages of the die surface due to stress are prevented and the average working life of the chip package is extended.
    Type: Application
    Filed: July 18, 2003
    Publication date: July 22, 2004
    Inventors: I-TSENG LEE, HSUEH KUO LIAO, JEN-TE TSENG
  • Publication number: 20020180057
    Abstract: A chip stack-type semiconductor package comprises: a substrate having a through hole penetrating there through, the substrate further having a plurality of first mounting pads and a plurality of second mounting pads; a first chip having a plurality of first bonding pads; a second chip having a plurality of second bonding pads, a backside surface of the second chip adhered onto a backside surface of the first chip, a active surface of the second chip adhered onto the substrate, the second bonding pads exposed to the inside of the through hole of the substrate; a plurality of first wires, connecting the first bonding pads and the first mounting pads; a plurality of second wires, connecting the second bonding pads and the second mounting pads; and a molding compound enveloping the first chip, the second chip, the first wires and the second wires.
    Type: Application
    Filed: August 10, 2001
    Publication date: December 5, 2002
    Inventors: I-Tseng Lee, Chih-Ming Chung