Patents by Inventor I-Tseng Lee
I-Tseng Lee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20220208559Abstract: Chip manufacturing, including: assembling at least two chips on a layer; and applying mold compound on the at least two chips to the sides and bottom including flowing around interconnects, thereby leaving the top of each of the at least two chips exposed.Type: ApplicationFiled: December 30, 2020Publication date: June 30, 2022Inventors: Ai-Tee Ang, I-Tseng Lee
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Publication number: 20180102296Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.Type: ApplicationFiled: December 11, 2017Publication date: April 12, 2018Applicant: Advanced Micro Device (Shanghai) Co., Ltd.Inventors: I-Tseng LEE, Yu-Ling HSIEH
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Patent number: 9870969Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.Type: GrantFiled: February 28, 2014Date of Patent: January 16, 2018Assignee: ADVANCED MICRO DEVICES (SHANGHAI) CO., LTD.Inventors: I-Tseng Lee, Yu-Ling Hsieh
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Patent number: 9214438Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.Type: GrantFiled: February 27, 2015Date of Patent: December 15, 2015Assignee: Advanced Micro Devices (Shanghai) Co., Ltd.Inventors: I-Tseng Lee, Yi Hsiu Liu
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Publication number: 20150171043Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.Type: ApplicationFiled: February 27, 2015Publication date: June 18, 2015Inventors: I-Tseng Lee, Yi Hsiu Liu
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Patent number: 8994191Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.Type: GrantFiled: January 21, 2014Date of Patent: March 31, 2015Assignee: Advanced Micro Devices (Shanghai) Co. Ltd.Inventors: I-Tseng Lee, Yi Hsiu Liu
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Publication number: 20140306338Abstract: The present invention relates to die-die stacking structure and the method for making the same. The die-die stacking structure comprises a top die having a bottom surface, a first insulation layer covering the bottom surface of the top die, a bottom die having a top surface, a second insulation layer covering the top surface of the bottom die, a plurality of connection members between the top die and the bottom die and a protection material between the first insulation layer and the second insulation layer. The plurality of connection members communicates the top die with the bottom die. The protection material bridges the plurality of connection members to form a mesh layout between the first insulation layer and the second insulation layer.Type: ApplicationFiled: January 21, 2014Publication date: October 16, 2014Inventors: I-Tseng Lee, Yi Hsiu Liu
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Publication number: 20140246223Abstract: The present invention relates to a substrate comprising a build-up and a solder resist layer disposed on the build-up. The solder resist layer has an upper surface facing away from the build-up. The solder resist layer has a plurality of grooves on its upper surface. The grooves of the solder resist layer can better eliminate or relieve the stress accumulated on large solder resist area induced by heat and/or material coefficient of thermal expansion mismatch of the substrate and thus can prevent and diminish warpage of the substrate or package.Type: ApplicationFiled: February 28, 2014Publication date: September 4, 2014Applicant: Advanced Micro Devices (Shanghai) Co., Ltd.Inventors: I-Tseng Lee, Yu-Ling Hsieh
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Publication number: 20120326299Abstract: Various semiconductor chip input/output structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided that includes applying a first polymer film to a side of a semiconductor chip and forming a first underbump metallization structure with at least a portion on the first polymer film. A second polymer film is applied on the first polymer film with an opening exposing a portion of the first underbump metallization structure.Type: ApplicationFiled: June 24, 2011Publication date: December 27, 2012Inventors: Roden R. Topacio, I-Tseng Lee
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Publication number: 20110299259Abstract: Various circuit board interconnect conductor structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is disclosed that includes forming a conductor post on a side of a circuit board. The conductor post includes an end projecting away from the side of the circuit board. A solder mask is applied to the side of the circuit board to cover the conductor post. A thickness of the solder mask is reduced so that a portion of the conductor post projects beyond the solder mask.Type: ApplicationFiled: June 4, 2010Publication date: December 8, 2011Inventors: Yu-Ling Hsieh, I-Tseng Lee, Yi-Hsiu Liu, Jen-Yi Tsai, Cheng-hua Fan
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Publication number: 20110278054Abstract: Various circuit board conductor structures and methods of making the same are disclosed. In one aspect, a method of manufacturing is provided. The method includes forming a first conductor pad on a circuit board. The first conductor pad includes a first notch and is adapted to couple to a first solder portion.Type: ApplicationFiled: May 14, 2010Publication date: November 17, 2011Inventors: I-Tseng Lee, Yi-Hsiu Liu, Jen-Yi Tsai
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Patent number: 7248477Abstract: A fan-shaped dissipating device, which is assembled on a chip of an erect PCB, has a conductive board, and a plurality of fins. The fins are respectively connected on an outside surface of the conductive board. Each of the fins has a top end and a bottom end. An interval between each two adjacent top ends of the fins is larger that between each two adjacent bottom ends of the fins. The fins are arranged in a radiating manner toward two sides from the bottom ends to the upper ends, therefore reducing the density of the accumulated air between the top ends of the fins because of rising hot air, and providing a better dissipating effect.Type: GrantFiled: October 6, 2004Date of Patent: July 24, 2007Assignee: Via Technologies, Inc.Inventors: I-Tseng Lee, Shih-Chang Ku
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Patent number: 7143509Abstract: A circuit board essentially comprises a first laminated structure, at least a first plated through hole, at least a second laminated structure, a middle dielectric layer and at least a second plated through hole is disclosed. The first laminated structure has at least three first circuit layers and at last two first dielectric layers. The first circuit layers and the first dielectric layers are alternately laminated and any two adjacent first circuit layers have a first dielectric layer disposed between them. The first plated through hole passes through the first laminated layer. The second laminated structure is laminated over the first laminated structure. The middle dielectric layer is disposed between the first laminated structure and the second laminated structure. The second plated through hole passes through the first laminated structure, the middle dielectric layer and the second laminated structure.Type: GrantFiled: May 31, 2005Date of Patent: December 5, 2006Assignee: VIA Technologies, Inc.Inventor: I-Tseng Lee
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Patent number: 7078794Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, a plurality of conductive wires and an insulating material is provided. The substrate has a first surface and a corresponding second surface. The substrate has a slot that penetrates the substrate. The chip is attached to the first surface of the substrate in a position that covers the slot. The conductive wires pass through the slot such that one end of each conductive wire is attached to a contact point on the chip while the other end of the conductive wire is attached to a contact point on the second surface of the substrate. The insulating material fills the space between the chip and the substrate and the slot so that the conductive wires and the bumps are enclosed.Type: GrantFiled: June 20, 2003Date of Patent: July 18, 2006Assignee: VIA Technologies, Inc.Inventor: I Tseng Lee
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Publication number: 20060112548Abstract: A circuit board essentially comprises a first laminated structure, at least a first plated through hole, at least a second laminated structure, a middle dielectric layer and at least a second plated through hole is disclosed. The first laminated structure has at least three first circuit layers and at last two first dielectric layers. The first circuit layers and the first dielectric layers are alternately laminated and any two adjacent first circuit layers have a first dielectric layer disposed between them. The first plated through hole passes through the first laminated layer. The second laminated structure is laminated over the first laminated structure. The middle dielectric layer is disposed between the first laminated structure and the second laminated structure. The second plated through hole passes through the first laminated structure, the middle dielectric layer and the second laminated structure.Type: ApplicationFiled: May 31, 2005Publication date: June 1, 2006Inventor: I-Tseng Lee
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Publication number: 20050237718Abstract: A fan-shaped dissipating device, which is assembled on a chip of an erect PCB, has a conductive board, and a plurality of fins. The fins are respectively connected on an outside surface of the conductive board. Each of the fins has a top end and a bottom end. An interval between each two adjacent top ends of the fins is larger that between each two adjacent bottom ends of the fins. The fins are arranged in a radiating manner toward two sides from the bottom ends to the upper ends, therefore reducing the density of the accumulated air between the top ends of the fins because of rising hot air, and providing a better dissipating effect.Type: ApplicationFiled: October 6, 2004Publication date: October 27, 2005Inventors: I-Tseng Lee, Shih-Chang Ku
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Patent number: 6946601Abstract: An electronic package with a passive component includes a circuit carrier, at least a passive component and an anisotropic conductive layer. The circuit carrier has at least a passive-component-pad set including multiple pads. The passive component has multiple electrodes placed over the corresponding pads of the passive-component-pad set. The anisotropic conductive layer is deposited between the electrodes and the pads.Type: GrantFiled: September 30, 2004Date of Patent: September 20, 2005Assignee: VIA Technologies Inc.Inventors: I-Tseng Lee, Jen-Te Tseng
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Patent number: 6919628Abstract: A stack chip package structure is provided. One principal feature of the structure is the formation of a few peripheral surfaces (e.g. ladder or lead-angle surfaces) at the bottom peripheral sections of a stack structure. When the stack structure is attached to a surface of a die through an adhesive layer, the thickness of the adhesive layer under a peripheral section of the stack structure is greater than a central region. Therefore, as the chip package is subjected to a thermal stress test, the adhesive layer under the peripheral sections of the stack structure is able to provide some buffering against thermal stress so that the stress concentration around the stack structure is reduced. Consequently, damages of the die surface due to stress are prevented and the average working life of the chip package is extended.Type: GrantFiled: July 18, 2003Date of Patent: July 19, 2005Assignee: Via Technologies, Inc.Inventors: I-Tseng Lee, Hsueh Kuo Liao, Jen-Te Tseng
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Publication number: 20040164389Abstract: A chip package structure comprising a substrate, a chip, a plurality of bumps, a plurality of conductive wires and an insulating material is provided. The substrate has a first surface and a corresponding second surface. The substrate has a slot that penetrates the substrate. The chip is attached to the first surface of the substrate in a position that covers the slot. The conductive wires pass through the slot such that one end of each conductive wire is attached to a contact point on the chip while the other end of the conductive wire is attached to a contact point on the second surface of the substrate. The insulating material fills the space between the chip and the substrate and the slot so that the conductive wires and the bumps are enclosed.Type: ApplicationFiled: June 20, 2003Publication date: August 26, 2004Inventor: I TSENG LEE
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Publication number: 20040140546Abstract: A stack chip package structure is provided. One principal feature of the structure is the formation of a few peripheral surfaces (e.g. ladder or lead-angle surfaces) at the bottom peripheral sections of a stack structure. When the stack structure is attached to a surface of a die through an adhesive layer, the thickness of the adhesive layer under a peripheral section of the stack structure is greater than a central region. Therefore, as the chip package is subjected to a thermal stress test, the adhesive layer under the peripheral sections of the stack structure is able to provide some buffering against thermal stress so that the stress concentration around the stack structure is reduced. Consequently, damages of the die surface due to stress are prevented and the average working life of the chip package is extended.Type: ApplicationFiled: July 18, 2003Publication date: July 22, 2004Inventors: I-TSENG LEE, HSUEH KUO LIAO, JEN-TE TSENG