Abstract: A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.

Abstract: A transaction level (TL) system power estimation method and system are provided. The method includes inserting at least a characteristic extractor into an electronic device of a target system. The characteristic extractor extracts at least a power characteristic of the electronic device when a TL simulation is proceeding. The power characteristic provided from the characteristic extractor is converted to at least a power consumption value by using a power model. The power consumption value is recorded into a power database, for analyzing power consumption of the whole target system. In some embodiments, the TL system power estimation method and system can be applied in the target system with dynamic power management. The TL system power estimation method and system also can be used with a high-level synthesizer to develop the power-aware electronic device in a short time.

Abstract: A data encryption/decryption system comprising a cryptographic interface operatively coupled between a host device and a data storage device is disclosed. The host and data storage devices include respective IDE controllers supporting full ATA protocol. The cryptographic interface includes a host device-side IDE controller and a data storage device-side IDE controller, each controller supporting partial ATA protocol. The cryptographic interface also includes a cipher engine adapted to transparently perform real time data ciphering during IDE/ATA data transfer between the host and data storage devices in conjunction with the host device-side IDE controller and the data storage device-side IDE controller.

Abstract: A data encryption/decryption system comprising a cryptographic interface operatively coupled between a host device and a data storage device is disclosed. The host and data storage devices include respective IDE controllers supporting full ATA protocol. The cryptographic interface includes a host device-side IDE controller and a data storage device-side IDE controller, each controller supporting partial ATA protocol. The cryptographic interface also includes a cipher engine adapted to transparently perform real time data ciphering during IDE/ATA data transfer between the host and data storage devices in conjunction with the host device-side IDE controller and the data storage device-side IDE controller.

Abstract: A full duplex DES cipher processor (DCP) supports to execute sixteen rounds of data encryption standard (DES) operation in four encryption modes and four decryption modes, namely: Electronic Code Book (ECB) mode, Cipher Block Chaining (CBC) mode, Cipher Feedback (CFB) mode, and Output Feedback (OFB) mode for both encryption and decryption. A DCP is composed of an I/O unit, an IV/key storage unit, a control unit, and an algorithm unit. The algorithm unit is used to encrypt/decrypt the incoming text message. The algorithm unit having a crypto engine allows encryption and decryption performed alternately, by sharing the same crypto engine. Since for crypto applications in communication services like T1, E1, V.35, the algorithm unit operation time is much shorter than the data I/O time; in other word, the algorithm unit is in the idle state mostly.