Abstract: A phase locked loop locks on to the phase of a high speed serial data stream. The phase locked loop includes a multiple bit latch, a multiple-stage voltage controlled oscillator, a phase detection circuit and a feedback circuit. The multiple-bit latch has a plurality of data latch elements and boundary-detect latch elements. Each latch element includes a latch input for receiving the serial data stream, a sample clock input and a latch output. The multiple-stage voltage controlled oscillator has a voltage control input, a plurality of sample clock outputs and an adjustable delay between each sample clock output. Each sample clock output is coupled to a corresponding sample clock input. The phase detection circuit is coupled to the latch outputs of the data and boundary-detect latch elements and has a phase control output. A feedback circuit is coupled between the phase control output and the voltage control input.

Abstract: Simple and efficient electronic circuits and methods are disclosed for better use of parallel optical interconnect system transmitting a plurality of dc NRZ data and an independent clock signal. The present invention dynamically compensates for the effects of the substrate temperature and aging behavior of the light emitters at both the transmitter and the receiver. In addition, a special arrangement of light emitters is used to reduce or avoid skew problems.

Abstract: Simple and efficient electronic circuits and methods are disclosed for better use of parallel optical interconnect system transmitting a plurality of dc NRZ data and an independent clock signal. The present invention dynamically compensates for the effects of the substrate temperature and aging behavior of the light emitters at both the transmitter and the receiver. In addition, a special arrangement of light emitters is used to reduce or avoid skew problems.

Abstract: A method and apparatus for decoding a specially encoded bit stream without the use of an external clock. A bit stream is encoded so that the relative lengths of the pulse widths between the transitions in the bit stream are indicative of the type bit being transmitted. A decoder receives the bit stream, measures the lengths of the pulses between the transitions, determines the type of bit by comparing the lengths, and stores the bit in a shift register. The bits can then be output in parallel form.