Abstract: Techniques for providing a modulation driver signal are disclosed. In an example, a modulation driver can include a first transistor configured to receive a first input signal having a first voltage swing, a second transistor coupled in series with the first transistor, and a third transistor configured to limit a third voltage swing across the second transistor. The second transistor can be configured to provide a representation of the first input signal as a first output signal of the modulator driver. The first output signal can have a second voltage swing greater than the first voltage swing.

Abstract: Apparatus and methods are provide for a multichannel clock and data recovery (CDR) device that shares information between channels. In an example, a multiple channel communication circuit can include a plurality of clock and data recovery (CDR) circuits, each CDR circuit of the plurality of CDR circuits associated with a channel of the multiple channel communication circuit. In certain examples, each CDR circuit can be configured to detect an incoming stream of data from the channel, to determine a setting of one or more parameters for correctly sampling the data from the incoming stream, and to share an indication of the setting of the one or more parameters to an adjacent CDR circuit of the plurality of CDR circuits.

Abstract: Apparatus and methods are provide for frame synchronization and clock and data recovery. In an example, a method can include receiving initial data of a stream of information, sampling the stream of information a plurality of times per unit interval to provide a plurality of sample intervals, integrating transition information for each sample interval, and selecting a sampling phase to sample each symbol of the stream of data using the integrated transition information.

Abstract: A power efficient device for driving a load comprising a low current path and a high current path, wherein the high current path is driven by a first voltage source. In order to accommodate larger turn on voltages of possible load devices while maintaining low power operation, an additional voltage source exceeding the voltage source in the high current path is introduced in the low current path.

Abstract: Apparatus and methods are provide for frame synchronization and clock and data recovery. In an example, a method can include receiving initial data of a stream of information, sampling the stream of information a plurality of times per unit interval to provide a plurality of sample intervals, integrating transition information for each sample interval, and selecting a sampling phase to sample each symbol of the stream of data using the integrated transition information.

Abstract: A power efficient device for driving a load comprising a low current path and a high current path, wherein the high current path is driven by a first voltage source. In order to accommodate larger turn on voltages of possible load devices while maintaining low power operation, an additional voltage source exceeding the voltage source in the high current path is introduced in the low current path.

Abstract: An eye quality monitoring system may include an eye quality monitor that includes a charge pump that is configured to output (a) a first charge in a first direction upon detection of a first transition of a sampled non-return-to-zero (NRZ) data signal in a first region of a unit interval of an eye pattern, and (b) a second charge in a second direction upon detection of a second transition of the sampled NRZ data signal in a second region of the unit interval of the eye pattern. The first direction is opposite from the second direction. The eye quality monitor is configured to form an eye quality output that relates to a quality of the eye pattern based on the first and second charges.

Abstract: An eye quality monitoring system may include an eye quality monitor that includes a charge pump that is configured to output (a) a first charge in a first direction upon detection of a first transition of a sampled non-return-to-zero (NRZ) data signal in a first region of a unit interval of an eye pattern, and (b) a second charge in a second direction upon detection of a second transition of the sampled NRZ data signal in a second region of the unit interval of the eye pattern. The first direction is opposite from the second direction. The eye quality monitor is configured to form an eye quality output that relates to a quality of the eye pattern based on the first and second charges.

Abstract: A data lock detection system may include a receiver configured to receive a data signal, a phase detector configured to output a phase detection output signal representative of the data signal with respect to a clock signal, and a lock detector configured to receive the phase detection output signal. The lock detector is configured to determine a presence of a frequency difference between the data signal and the clock signal and output a lock determination output signal that indicates if the data signal is locked or unlocked with the clock signal.

Abstract: A data lock detection system may include a receiver configured to receive a data signal, a phase detector configured to output a phase detection output signal representative of the data signal with respect to a clock signal, and a lock detector configured to receive the phase detection output signal. The lock detector is configured to determine a presence of a frequency difference between the data signal and the clock signal and output a lock determination output signal that indicates if the data signal is locked or unlocked with the clock signal.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Abstract: A driver device for a laser includes a control device configured to generate a control current, an NPN differential amplifier connected to the control device and configured to superimpose a modulation current onto the control current to generate a combined current, and a laser activation switch coupled to the output of the NPN differential amplifier, the laser activation switch operating the laser utilizing the combined current. Also described herein is a communication system including a driver device.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Abstract: A driver device for a laser includes a control device configured to generate a control current, an NPN differential amplifier connected to the control device and configured to superimpose a modulation current onto the control current to generate a combined current, and a laser activation switch coupled to the output of the NPN differential amplifier, the laser activation switch operating the laser utilizing the combined current. Also described herein is a communication system including a driver device.

Abstract: Embodiments of a device and circuit implementing a digitally controlled oscillator with reduced analog components. In an example, the digitally controlled oscillator can include a phase accumulator controlled by a stall circuit to selective stall the phase accumulator. In some examples, the digitally controlled oscillator can include a phase select circuit to select multiple phases of a phase select circuit based on the output of the phase accumulator. In some examples, these selected phases can then be used by a phase interpolator to generate a synthetic clock signal.

Abstract: This document describes systems and methods for providing an interface apparatus for a photodiode, including a fully differential transimpedance amplifier. A first transimpedance amplifier input is coupled to a regulated bias voltage through the photodiode. A second transimpedance amplifier input is coupled to the regulated bias voltage through an on-chip programmably adjustable capacitor. The programmably adjustable capacitor is adjusted such that its capacitance value substantially matches that of the reverse-biased photodiode. This reduces or eliminates mismatch in coupling of noise from the regulated bias voltage onto the first and second inputs of the transimpedance amplifier.

Abstract: A variable gain amplifier is provided by including a gain control transistor with a differential amplifier. The differential amplifier has a first and second transistor each coupled to data inputs, which can receive a differential data signal. The gain control transistor is coupled between the drains of the first and second transistors. Control voltages are used to shunt differential current through the gain control transistor, providing variable gain with the maximum gain occurring when the control signals turn the gain control transistor off. A constant bias current is maintained by a pair of cascode transistors in parallel coupled to the sources of the first and second transistor.

Abstract: Systems, devices and methods are provided for precisely and responsively compensating for deterministic jitter. One aspect of the present subject matter is a circuit for improving a phase lock of a timing signal for a receiver. One embodiment includes a sample and hold circuit, a decision logic module, and a switch. The sample and hold circuit is adapted to receive and hold a phase signal that represents a signal from a phase detector of the receiver. The switch is adapted to controllably pass the phase signal from the sample and hold circuit. The passed phase signal is capable of being used in adjusting the timing signal for the receiver. The decision logic module is adapted to detect good signal transitions, and actuate the switch to pass the phase signal for good signal transitions. Other aspects are provided herein.

Abstract: This document describes systems and methods for aligning an optical fiber to a light source or detector. In one example, the alignment is based on a measured amplitude. In another example, the alignment is based on a measured jitter. In another example, the alignment is based on a combination of the measured amplitude and the measured jitter. In another example, the alignment is based on a combination of a measured quiescent response in combination with at least one of the measured amplitude and the measured jitter. The alignment may be performed manually or automatically. By securing the optical fiber in a properly aligned position, improved coupling to the light source or detector is obtained.