Abstract: A ?? frequency to digital converter includes digital feedback to an accumulator in a ring phase calculator that provides the converter output, which reduces implantation complexity. Digital gain correction is applicable to dual mode ring oscillator converters and charge pump converters, provides compensation for forward path gain error and eliminates the need to include analog gain correction in feedback. Asynchronous sampling includes correction logic to compensate for arbitrary initial conditions. A digitally-controlled oscillator (DCO) control technique causes the DCO frequency to increase or decrease by changing the state of one its frequency control elements at a time.

Abstract: A ?? frequency to digital converter includes digital feedback to an accumulator in a ring phase calculator that provides the converter output, which reduces implantation complexity. Digital gain correction is applicable to dual mode ring oscillator converters and charge pump converters, provides compensation for forward path gain error and eliminates the need to include analog gain correction in feedback. Asynchronous sampling includes correction logic to compensate for arbitrary initial conditions. A digitally-controlled oscillator (DCO) control technique causes the DCO frequency to increase or decrease by changing the state of one its frequency control elements at a time.

Abstract: A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.

Abstract: A digital fractional-N phase locked loop (PLL) with multi-rate dynamic element matching (DEM) and an adaptive mismatch-noise cancellation (MNC) is provided. The PLL includes a phase error to digital converter and a digital loop filter to suppress quantization noise of the phase error to digital converter and drive a digitally controlled oscillator. A digitally controlled oscillator (DCO) with a multi-rate DEM encoder includes an integer bank of frequency control elements (FCE) and a fractional bank of frequency control elements. Adaptive mismatch-noise cancellation logic operates to cancel DCO phase error arising from frequency control element (FCE) static and dynamic mismatch error by estimating ideal MNC coefficient values during PLL normal operation, estimating MNC coefficient errors at each sample time, and updating the MNC coefficient values to approach zero (FCE) static and dynamic mismatch error.

Abstract: A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic. Preferred embodiments of the invention include circuit-level techniques that provide better spurious tone performance and very low phase noise with lower power dissipation and supply voltage than prior digital PLLs known to the inventors.

Abstract: A frequency-to-digital-converter based PLL (FDC-PLL) that implements the functionality of a charge pump and analog-to-digital converter (ADC) with a dual-mode ring oscillator (DMRO) and digital logic.

Abstract: Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device.

Abstract: A continuous-time delta-sigma modulator for analog-to-digital conversion includes a pair of pseudo-differential signal paths including a pair of pseudo-differential signal paths including current-controlled ring oscillators as the load of open-loop common-source amplifiers that are driven by an analog input signal. The signal path produces digital values by sampling the open-loop current-controlled ring oscillators. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects digital values based upon the nonlinear distortion coefficients.

Abstract: Certain aspects of the present disclosure support a method and apparatus for foreground and background bandwidth calibration in a frequency-do-digital converter based phase-locked loop (FDC-PLL) device.

Abstract: An oscillating circuit with linear gain is presented. The oscillating circuit may include a relaxation oscillator and a current compensation block. The relaxation oscillator includes a capacitor, a pair of resistors operative to deliver a first current to the capacitor, and a first current source adapted to generate the first current having a first predefined level. The current compensation block includes a second current source, and a pair of cross-coupled transistors coupled to the second current source and adapted to steer a current exceeding the first predefined level in the relaxation oscillator away from the capacitor and to the second current source. The proposed oscillating circuit generates an output signal which has a linear gain over a wide tuning range.

Abstract: An oscillating circuit with linear gain is presented. The oscillating circuit may include a relaxation oscillator and a current compensation block. The relaxation oscillator includes a capacitor, a pair of resistors operative to deliver a first current to the capacitor, and a first current source adapted to generate the first current having a first predefined level. The current compensation block includes a second current source, and a pair of cross-coupled transistors coupled to the second current source and adapted to steer a current exceeding the first predefined level in the relaxation oscillator away from the capacitor and to the second current source. The proposed oscillating circuit generates an output signal which has a linear gain over a wide tuning range.

Abstract: A continuous-time delta-sigma modulator for analog-to-digital conversion includes a pair of pseudo-differential signal paths including a pair of pseudo-differential signal paths including current-controlled ring oscillators as the load of open-loop common-source amplifiers that are driven by an analog input signal. The signal path produces digital values by sampling the open-loop current-controlled ring oscillators. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path.

Abstract: An embodiment provides a continuous-time delta-sigma modulator for analog-to-digital conversion. The modulator includes a signal path generating including a ring voltage controlled oscillator driven by an analog input signal. The signal path produces digital values by sampling the ring voltage controlled oscillator. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects the digital values based upon determined nonlinear distortion coefficients. Preferred embodiment ADC ?? modulators do not require any analog integrators, feedback DACs, comparators, or reference voltages, and do not require a low jitter clock.

Abstract: An embodiment provides a continuous-time delta-sigma modulator for analog-to-digital conversion. The modulator includes a signal path generating including a ring voltage controlled oscillator driven by an analog input signal. The signal path produces digital values by sampling the ring voltage controlled oscillator. A calibration circuit measures nonlinear distortion coefficients in a replica of the signal path. A nonlinearity corrector corrects the digital values based upon determined nonlinear distortion coefficients. Preferred embodiment ADC ?? modulators do not require any analog integrators, feedback DACs, comparators, or reference voltages, and do not require a low jitter clock.

Abstract: An embodiment of the invention is a circuit for adaptive phase noise cancellation for a fractional-N PLL. A preferred embodiment employs a split loop filter architecture. Two loop filter halves separately drive half-sized parallel varactors in a voltage controlled oscillator (VCO) and also drive a differential-input lowpass frequency selective circuit, e.g., a differential-input integrator in a least mean squared (LMS) feedback loop. The output of the differential-input lowpass frequency selective circuit controls the gain matching of a phase noise cancellation path to minimize phase noise arising from quantization error associated with the sequence of divider modulus values in the fractional-N PLL. The two varactor capacitances add together in the VCO tank, so the VCO frequency depends on the common-mode loop filter voltage and is relatively insensitive to differential-mode voltage.

Abstract: A successive requantizer, which serves as a replacement for a ?? modulator in a fractional-N PLL or a DAC, and avoids spurious tone problems, thereby circumventing the tradeoffs that result from reliance on the common approach of making highly linear analog circuitry to avoid spurious tones. A successive requantizer fractional-N PLL of the invention has the potential to reduce power consumption and the cost of commercial communication devices. The successive requantizer performs digital quantization one bit at a time in such a way that the quantization noise can he engineered to have desirable properties such as non-linearity robustness. The successive requantizer is applicable to most high-performance digital communication systems, such as cellular telephone handsets and wireless local and metropolitan area network transceivers.

Abstract: The invention is directed to digital generation of RF signals. In the digital domain, digital RF signals are converted to the digital signals clocked at a high speed clock that is phase-synchronized with the RF carrier. A band-pass delta-sigma modulator produces a bit stream from the converted digital signals.

Abstract: An embodiment of the invention is a successive requantizer, which serves as a replacement for a ?? modulator in a fractional-N PLL or a DAC, and avoids the above-mentioned spurious tone problem, thereby circumventing the tradeoffs that result from reliance on common approach of making highly linear analog circuitry to avoid spurious tones. A successive requantizer fractional-N PLL of the invention has the potential to reduce power consumption and the cost of commercial communication devices. A successive requantizer of the invention performs digital quantization one bit at a time in such a way that the quantization noise can be engineered to have desirable properties such as non-linearity robustness. The invention is applicable to most high-performance digital communication systems, such as cellular telephone handsets and wireless local and metropolitan area network transceivers.

Abstract: An embodiment of the invention is a circuit for adaptive phase noise cancellation for a fractional-N PLL. A preferred embodiment employs a split loop filter architecture. Two loop filter halves separately drive half-sized parallel varactors in a voltage controlled oscillator (VCO) and also drive a differential-input lowpass frequency selective circuit, e.g., a differential-input integrator in a least mean squared (LMS) feedback loop. The output of the differential-input lowpass frequency selective circuit controls the gain matching of a phase noise cancellation path to minimize phase noise arising from quantization error associated with the sequence of divider modulus values in the fractional-N PLL. The two varactor capacitances add together in the VCO tank, so the VCO frequency depends on the common-mode loop filter voltage and is relatively insensitive to differential-mode voltage.

Abstract: The invention provides methods and devices for estimating power amplifier nonlinearity using simple correlation techniques. Methods and devices of the invention can monitor a power amplifier that has digitally modulated inputs and an output containing more than one signal stream. A preferred method of the invention creates a test signal by forming the products of several pseudorandom noise sequences from the digitally modulated inputs to the power amplifier. Nonlinear contributions of the power amplifier output are determined by cross-correlating the test signal and the total output signal of the power amplifier. In preferred embodiments, the determined nonlinear contributions of the power amplifier are used to introduce corrective predistortion in the power amplifier.