Patents by Inventor Ian A. McCallum

Ian A. McCallum has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250072024
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a transistor with a thermal plug and methods of manufacture. The structure includes: a semiconductor substrate; a gate structure over the semiconductor substrate; a source region on a first side of the gate structure; a drain region on a second side of the gate structure; and a thermal plug extending from a top side of the semiconductor substrate into an active region of the semiconductor substrate.
    Type: Application
    Filed: August 23, 2023
    Publication date: February 27, 2025
    Inventors: Alvin J. Joseph, Mark D. Levy, Rajendran Krishnasamy, Johnatan A. Kantarovsky, Ajay Raman, Ian A. McCallum-Cook
  • Patent number: 9831194
    Abstract: Structures for a chip, as well as methods of fabricating such chip structures. The chip including a portion of a substrate, an active circuit region associated with the portion of the substrate, an interconnect structure on the active circuit region, and a crackstop extending through the interconnect structure. A groove extends through the interconnect structure to the substrate at a location exterior of the crackstop. A stress-containing layer is formed on at least a portion of the groove.
    Type: Grant
    Filed: July 6, 2016
    Date of Patent: November 28, 2017
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Tom C. Lee, Cathryn J. Christiansen, Ian A. McCallum-Cook, Anthony K. Stamper
  • Patent number: 9576899
    Abstract: Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate. Trenches that surround the modified region and that penetrate into the semiconductor substrate to a depth greater than a depth of the modified region are formed in the modified region so as to define a fuse link of the electrical fuse. The substrate is removed from beneath the fuse link with a selective etching process that removes the semiconductor substrate with a first etch rate that is higher than a second etch rate of the modified region.
    Type: Grant
    Filed: June 23, 2015
    Date of Patent: February 21, 2017
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Vibhor Jain, Qizhi Liu, Ian A. McCallum-Cook
  • Publication number: 20160379930
    Abstract: Electrical fuses and methods for forming an electrical fuse. A semiconductor substrate is implanted to define a modified region in the semiconductor substrate. Trenches that surround the modified region and that penetrate into the semiconductor substrate to a depth greater than a depth of the modified region are formed in the modified region so as to define a fuse link of the electrical fuse. The substrate is removed from beneath the fuse link with a selective etching process that removes the semiconductor substrate with a first etch rate that is higher than a second etch rate of the modified region.
    Type: Application
    Filed: June 23, 2015
    Publication date: December 29, 2016
    Inventors: Vibhor Jain, Qizhi Liu, Ian A. McCallum-Cook
  • Patent number: 9444123
    Abstract: A battery pack includes a plurality of prismatic format batteries in a stacked configuration. Flexible graphite sheet heat spreaders are interposed between adjacent prismatic batteries in the stack. A heat sink extends the length of the stack of prismatic format batteries. Both heat spreader major surfaces contact the heat sink at contact areas and thereby extend into the heat sink by at least 30 percent of the thru-thickness of the heat sink.
    Type: Grant
    Filed: October 30, 2015
    Date of Patent: September 13, 2016
    Assignee: GrafTech International Holdings Inc.
    Inventors: Richard A. Beyerle, II, Ian A. McCallum, Martin D. Smalc, Jonathan A. Taylor, Ryan J. Wayne
  • Patent number: 9383404
    Abstract: A high resistivity substrate final resistance test structure, methods of manufacture and testing processes are disclosed. The test structure includes spaced apart implants extending into a high resistivity wafer in at least one kerf region of the wafer. The test structure further includes contacts in direct electrical contact to each of the spaced apart implants.
    Type: Grant
    Filed: December 5, 2014
    Date of Patent: July 5, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Jeffrey P. Gambino, Eric D. Johnson, Ian A. McCallum-Cook, Richard A. Phelps, Anthony K. Stamper, Michael J. Zierak
  • Publication number: 20160161545
    Abstract: A high resistivity substrate final resistance test structure, methods of manufacture and testing processes are disclosed. The test structure includes spaced apart implants extending into a high resistivity wafer in at least one kerf region of the wafer. The test structure further includes contacts in direct electrical contact to each of the spaced apart implants.
    Type: Application
    Filed: December 5, 2014
    Publication date: June 9, 2016
    Inventors: Jeffrey P. GAMBINO, Eric D. JOHNSON, Ian A. MCCALLUM-COOK, Richard A. PHELPS, Anthony K. STAMPER, Michael J. ZIERAK
  • Publication number: 20160049704
    Abstract: A battery pack includes a plurality of prismatic format batteries in a stacked configuration. Flexible graphite sheet heat spreaders are interposed between adjacent prismatic batteries in the stack. A heat sink extends the length of the stack of prismatic format batteries. Both heat spreader major surfaces contact the heat sink at contact areas and thereby extend into the heat sink by at least 30 percent of the thru-thickness of the heat sink.
    Type: Application
    Filed: October 30, 2015
    Publication date: February 18, 2016
    Inventors: Richard A. Beyerle, II, Ian A. McCallum, Martin D. Smalc, Jonathan A. Taylor, Ryan J. Wayne
  • Publication number: 20110020665
    Abstract: A surface finishing and coating methodology that provides a superior looking aluminum product with acceptable corrosion performance for outdoor use. In one embodiment, a coating of high purity aluminum is applied first to an aluminum article or product via cold or thermal spray and the mechanical surface modification (e.g., polishing, buffing, brushing, etc.) is clone second. The resulting product has the desirable light weight and mechanical properties of aluminum with the chosen look and performance of the high purity aluminum coating. The aluminum product to be coated may be obtained by extrusion, forging, casting, or rolling.
    Type: Application
    Filed: June 13, 2008
    Publication date: January 27, 2011
    Applicant: ALCOA INC.
    Inventors: Daniel L. Serafin, Ian A. McCallum, Roger W. Kaufold, Robert E. Bombalski, Luis Fanor Vega, Donald Robert Smith