Abstract: Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO.

Abstract: Certain aspects of the present disclosure support a method and apparatus for fast frequency throttling and re-locking in a phase-locked loop (PLL) device. Aspects of the present disclosure present a method and apparatus for operating in an open loop control (OLC) mode of the PLL device for generating a periodic signal. During the OLC mode, clocking of circuitry interfaced with a digitally-controlled oscillator (DCO) of the PLL device can be disabled. A PLL output frequency associated with the periodic signal generated by the DCO can be controlled directly through a digital control word input into the DCO.

Abstract: A novel mismatched-shaping DAC architecture is described. The inventive DAC partially spectrally shapes data conversion errors. In accordance with the present invention, the DAC mismatch-shaping function is fully effective for input signal amplitude levels that are relatively low (i.e., close to mid-scale), however, the mismatch-shaping function is not fully effective for input signal amplitude levels that are relatively high. This results in the simplification in complexity, reduced power dissipation, and shortened propagation delays associated with the mismatch-shaping DAC digital logic circuitry. Exemplary delta-sigma ADC and DAC architectures adapted for use with the present inventive partial mismatch-shaping DAC are also described.