Abstract: A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.

Abstract: Guidance provision to the creation of an electronic design is facilitated through a method that includes facilitating interactive exploration of the electronic design by a designer to aid the designer in formulating his/her guidance, and facilitating the designer in interactively providing the formulated guidance. In one embodiment, facilitation of interactive exploration by the designer include facilitating interactive cross-probing into a number of issues about the design, including generated candidate architectures for the design. In one embodiment, the issues available for cross probing include inter-dependencies of data and mobility of operations of the design, as well as occupation of hardware resources for the generated candidate architectures. In one embodiment, Gantt diagrams are employed to facilitate navigation by the designer in performing the interactive cross probing. Gantt diagrams graphically representing the generated candidate architectures are selectively presented to the designer.

Abstract: A tool is disclosed that allows a hardware designer using a behavioral synthesis tool to view a calculated execution time for a group of related loops identified in source code describing a hardware design circuit. Further, a designer can then interactively unroll and/or pipeline a selected loop without having to modify the source code description of the circuit. Using a graphical user interface (GUI), the designer can modify the loop design easily and see the results of the new loop configuration without having to generate the RTL code, perform RTL synthesis, etc. For example, the designer can readily view the relative loop execution time of the circuit to better determine whether the design is acceptable. Additionally, the designer can execute an area-versus-latency analysis, and, if the analysis is not satisfactory, the designer can unroll and or pipeline selected loops using the GUI.