Abstract: A switched capacitor circuit is described which is programmable so that its function can be set by a user. Thus, control circuitry and selection circuitry are provided to enable one of a plurality of alternative control signals to be provided to switch circuits of the switched capacitor circuit. In this way, the function of the switched capacitor circuits can be altered. Where there are a plurality of switched capacitor circuits connected in an array, the topology of the array can be altered by suitably routing particular input signals to particular outputs by selecting the control signals to control the switched circuits. A field programmable array of this type is also described.

Abstract: An integrator circuit which uses switched current techniques and includes a first current memory cell (T31,T32, S31, C31) a second current memory cell (T33, T34, C32, S32, T35) and a third (correcting) current memory cell (T36, S33, C33). An input current signal is fed to input (30) and a switch (S30) is closed during the .phi. portion of each sampling period, as is the switch (S31) in the first current memory cell. The other switches (S32, S33) are closed during the .phi. portion of each sampling period. During the .phi. portion transistor (T31) acts as a current source producing the current applied to it in the preceding .phi. portion. This is subtracted from the current produced by the output of the second current memory cell (T34) and the difference is stored in the third current memory cell (T36, S33, C33). During the next .phi. portion transistor (T36) acts a current source correcting the feedback current fed to the input (T31) of the first current memory cell.

Abstract: A circuit arrangement for processing sampled analog electric signals includes a low voltage cascode current mirror circuit arrangement having an input branch comprising first and second FETs (T1,T3) and an output branch comprising third and fourth FETs (T2,T4). In order to provide the correct bias potential of V.sub.t +2V.sub.on at the gate electrodes of the second and fourth FETs (T3,T4) a second output branch comprising two further FETs (T5,T6) and a further current mirror circuit comprising two other FETs (T7,T8) pass a current through a diode connected FET (T9) so that it produces a voltage V.sub.t +V.sub.on. If this current is equal to the input current, then the diode connected FET (T9) is constructed to have a gate width to length ratio of one quarter of that of the cascode connected transistors (T3,T4). The current mirror circuit may be incorporated into current scaling and current memory circuits for signal current manipulation.