Abstract: A high-speed bus system for a computer is constructed of a network of buses with parallel bit lines, each bus of which operates independently and supports serial packet communications, wherein transmit agents and receive agents associated with each communicating element in the bus system are connected to the bus system. Each transmit agent controls a single bus for transmission and each receive agent is connected to all other buses for reception in a diagonal topology. The architecture is based on use of a buffering element at each node in the bus structure, herein referred to as a cell bus interface (CBI) unit. Based on header data containing address information appended as part of a packet cell by a transmitting transmit agent, each receive agent decides whether the information provided on any bus is intended for it as a destination agent.