Abstract: A system and a method for determining an attitude of a device undergoing dynamic acceleration is presented. A first attitude measurement is calculated based on a magnetic field measurement received from a magnetometer of the device and a first acceleration measurement received from a first accelerometer of the device. A second attitude measurement is calculated based on the magnetic field measurement received from the magnetometer of the device and a second acceleration measurement received from a second accelerometer of the device. A correction factor is calculated based at least in part on a difference of the first attitude measurement and the second attitude measurement. The correction factor is then applied to the first attitude measurement to produce a corrected attitude measurement for the device.

Abstract: A disk drive assembly includes a disk drive, one or more accelerometers, a control circuit, and an adaptive feed forward circuit. The one or more accelerometers generate acceleration signals that are used to detect rotational vibration (RV) events on the disk drive. The control circuit is configured to: generate one or more control signals, which are based on a control signal from a host system and a compensation signal from the adaptive feed forward circuit, and generate a position error signal (PES) that indicates an error in a position of a disk drive head relative to a center of a track. The adaptive feed forward circuit generates the compensation signal, which compensates for the detected RV events based on the acceleration signals and the PES. The compensation signal accounts for self-induced RV events generated by a SEEK operation that repositions the head to a new track, wherein feed forward adaption is not disturbed by the SEEK operation.

Abstract: Methods and systems for gaming over a network or communications medium such as via the Internet. In specific embodiments, a real video gaming experience is generated by for a player at a client system from a sequence of real world derived chance events and associated video clips. The server system optionally provides a sequence in an encoded format and the sequence is delivered to the client where the client uses the sequence to create a game of chance for a player.

Abstract: An intelligent electric bicycle includes a pedal drive unit, a power assist unit, a tread detector for detecting treading action on the pedal drive unit, a throttle unit for controlling output power of the power assist unit, a speed sensor, and a controller coupled electrically to the power assist unit, the tread detector, the throttle unit and the speed sensor. The controller operates in one of a user-controlled power distribution mode, an automatic drive mode and a cruise control mode according to the detected states of the pedal drive unit and the throttle unit and the moving speed of the bicycle.

Abstract: An intelligent electric bicycle includes a pedal drive unit, a power assist unit, a tread detector for detecting treading action on the pedal drive unit, a throttle unit for controlling output power of the power assist unit, a speed sensor, and a controller coupled electrically to the power assist unit, the tread detector, the throttle unit and the speed sensor. The controller operates in one of a user-controlled power distribution mode, an automatic drive mode and a cruise control mode according to the detected states of the pedal drive unit and the throttle unit and the moving speed of the bicycle.

Abstract: A residual power indicator includes a current detector for monitoring current consumption of a storage battery, and a processor unit for calculating consumed power of the storage battery. The processor unit includes a memory device for recording a reference value corresponding to the residual power of the storage battery. The reference value in the memory device is periodically updated by the processor unit to reflect actual residual power of the storage battery. A display unit is controlled by the processor unit so as to provide a visual indication corresponding to the reference value in the memory device.

Abstract: A computer system (8) comprising a central processing unit (12) and a memory hierarchy. The memory hierarchy comprises a first cache memory (16) and a second cache memory (26). The first cache memory is operable to store non-pixel-information, wherein the non-pixel information is accessible for processing by the central processing unit. The second cache memory is higher in the memory hierarchy than the first cache memory, and has a number of storage locations operable to store non-pixel information (26b) and pixel data (26a). Lastly, the computer system comprises cache control circuitry (24) for dynamically apportioning the number of storage locations such that a first group of the storage locations are for storing non-pixel information and such that a second group of the storage locations are for storing pixel data.

Abstract: Circuits, systems, and methods relating to operating a computer system operable in a system manager mode (24). The method includes various steps. The first step (34) occurs during operation of the computer system (10) at a time other than start-up, and receives user power management data from a user of the computer system. The second step (38) stores the user power management data in memory space (30) accessible by the system management mode. The third step (40) accesses the user power management data from the memory space. Finally, the fourth step (42) controls at least one peripheral (14, 16, 18, 20) of the computer system in response to the accessed user power management data.

Abstract: A microprocessor-based system (2) is disclosed, based on an x86-architecture microprocessor (5). The system includes a memory address space (30) and a input/output address space (40), where input/output operations are performed in an I/O mapped manner. According to a first embodiment of the invention, burstable access is performed to areas of the main memory (32) which are blocked from cache access, by the microprocessor (5) asserting the cache request signal (CACHE#) in combination with the control signal (M/IO#) indicating that an I/O operation is requested. The memory controller (10) interprets this combination as a burst request to the non-cacheable memory location (32), indicates the grant of burst access by asserting the cache acknowledge control signal (KEN#), and the burst memory access is then effected.

Abstract: A microprocessor-based data processing system (2) in which asynchronous bus transactions are performed is disclosed. The disclosed embodiments include one or more microprocessors (5) of the x86-architecture type, compatible with the P54C bus protocol, preferably Pentium-compatible microprocessors, as the central processing units (CPUs) of the system. A CPU (5.sub.r) requests an asynchronous bus transaction, in a first disclosed embodiment, by presenting a combination of control signals that is unused in conventional x86-architecture systems; the controller chipset (27) determines whether the transaction may be performed in an asynchronous manner, and later returns an acknowledge or non-acknowledge code to the requesting CPU (5.sub.r). The microprocessors (5) include certain pins, in this first embodiment, corresponding to conventional Pentium-compatible output pins but which now have receiver circuitry for receiving the acknowledge and non-acknowledge codes, along with the transaction identifier.

Abstract: In a method embodiment (34), the method operates a computer system (10) having a type of configuration and including a single integrated circuit microprocessor (24). The microprocessor operates in response to codes and has an instruction set. The method involves various steps, including determining (40) the type of the configuration. In response to the type of the configuration, the method selects (42) a set of patch codes from a plurality of sets of patch codes. The method also issues (54) a patch request instruction from the instruction set, and it stores (56) the selected set of patch codes to a memory space accessible by the microprocessor.

Abstract: A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

Abstract: An integrated circuit includes a single chip (102) that has a microprocessor (702), a memory controller unit (718), an internal bus (714) connecting the microprocessor (702) and the memory controller unit (718), and an external bus to internal bus interface circuit (716). The microprocessor (102) occupies a substantially rectangular region on a substrate (802). The memory controller unit (718) occupies a first strip along one side of the microprocessor unit (702) accessible via the bond pads broadside to the first strip. Other circuits, systems, and methods are disclosed.

Abstract: A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.

Abstract: A microprocessor device (102) includes a central processing unit (702) having a clock input, a clock generator (OSC, PLL) of clock pulses, a logic circuit (708) having an output to supply a clock control signal (SUSP), and a clock gate (3610) fed by the clock pulses and having a clock gate output (CPU.sub.-- CLK) coupled to the clock input of the central processing unit. The clock gate (3610) responds to the clock control signal (SUSP) to prevent said clock pulses (CPU.sub.-- CLK) from reaching the central processing unit within one clock cycle of a change in said clock control signal. Other devices, systems and methods are also disclosed.