Abstract: Provided is an enclosure for use in a modular storage system, the enclosure comprising a plurality of drive bays, a controller canister, an expansion canister, and a midplane connecting the drive bays to the canisters, wherein the controller canister occupies a greater volume of the enclosure than the expansion canister.

Abstract: Provided is an enclosure for use in a modular storage system, the enclosure comprising a plurality of drive bays, a controller canister, an expansion canister, and a midplane connecting the drive bays to the canisters, wherein the controller canister occupies a greater volume of the enclosure than the expansion canister.

Abstract: A method of controlling data transfers between a volatile memory and a non-volatile storage, the volatile memory being on a memory device operatively coupled to a computer system, the data transfers comprising: storing data from the volatile memory to the non-volatile storage when a power source of the computer system fails, the method comprising following re-establishment of the previously failed power source, the step of: selectively restoring data from the non-volatile storage to the volatile memory by a controller software after restart operations.

Abstract: A Redundant Array of Independent Disks (RAID) controller receives new data that is to be written, wherein the new data is indicated in blocks of a first block size. The RAID controller reads old data, and old parity that corresponds to the old data, stored in blocks of a second block size that is larger in size than the first block size. The RAID controller computes new parity based on the new data, the old data, and the old parity. The RAID controller writes the new data and the new parity aligned to the blocks of the second block size, wherein portions of the old data that are not overwritten by the RAID controller are also written to the blocks of the second block size.

Abstract: A method of controlling data transfers between a volatile memory and a non-volatile storage, the volatile memory being on a memory device operatively coupled to a computer system, the data transfers comprising: storing data from the volatile memory to the non-volatile storage when a power source of the computer system fails, the method comprising following re-establishment of the previously failed power source, the step of: selectively restoring data from the non-volatile storage to the volatile memory by a controller software after restart operations.

Abstract: Logic is provided for increasing energy-efficiency of a data processing system. First logic continuously checks a plurality of I/O ports for incoming workload. Responsive to the incoming workload being lower than a low workload threshold for a current operating frequency, second logic reduces an operating frequency of the processor. Responsive to the incoming workload being higher than a high workload threshold, the second logic increases the operating frequency of the processor.

Abstract: Logic is provided for increasing energy-efficiency of a data processing system. First logic continuously checks a plurality of I/O ports for incoming workload. Responsive to the incoming workload being lower than a low workload threshold for a current operating frequency, second logic reduces an operating frequency of the processor. Responsive to the incoming workload being higher than a high workload threshold, the second logic increases the operating frequency of the processor.

Abstract: Provided is an enclosure for use in a modular storage system, the enclosure comprising a plurality of drive bays, a controller canister, an expansion canister, and a midplane connecting the drive bays to the canisters, wherein the controller canister occupies a greater volume of the enclosure than the expansion canister.

Abstract: Logic is provided for increasing energy-efficiency of a data processing system. First logic continuously checks a plurality of I/O ports for incoming workload. Responsive to the incoming workload being lower than a low workload threshold for a current operating frequency, second logic reduces an operating frequency of the processor. Responsive to the incoming workload being higher than a high workload threshold, the second logic increases the operating frequency of the processor.

Abstract: According to one general embodiment of the present invention, there is provided a computer program product for reducing incidence of errors in connections between a power consumer apparatus operable to draw a load and a power supply apparatus capable of varying the power supplied, the computer program product comprising: a computer readable storage medium having computer readable program code embodied therewith, the computer readable program code comprising: computer readable program code configured to generate at the power consumer apparatus an identifiable pattern in a load to be drawn from a power supply connection to a power supply apparatus; and computer readable program code configured to monitor at the power consumer apparatus for a change in the load corresponding to the pattern, the monitoring being performed across a signal connection to the power supply apparatus; wherein a positive result of the monitoring indicates a correct configuration. Additional embodiments are also presented.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: An apparatus for a node of a peer-to-peer network having a plurality of nodes comprises one or more I/O adapters; a cache component; one or more inter-node routing components; a memory mapping component for presenting to the I/O adapters a single address space mapped across a plurality of memory elements each associated with the cache component; and a direct memory access component for performing a memory operation on the memory elements via the memory mapping component on behalf of the I/O adapters.

Abstract: A high performance data storage subsystem which is suitable for connection to a data processing system. The main functional units of the subsystem are (i) a host adapter, (ii) a device controller and (iii) at least one direct access storage device (DASD). The functional units are interconnected by dedicated, point to point, full duplex serial links over which commands and data are transmitted in the form of packets. The serial links also support packet multiplexing which allows commands transmitted over the serial link to be multiplexed with read or write data being transferred from and to the devices. A basic configuration of the subsystem comprises an adapter connected via a serial link to a controller which is in turn connected by four serial links to four DASDs. However the subsystem architecture described allows each adapter to be connected to up to four controllers, thus allowing a maximum of sixteen devices to be attached to one adapter.

Abstract: A data storage subsystem and method for transferring data from a storage subsystem to a connected host data processing system are described. The subsystem comprises a device controller connected to one or more direct access storage devices e.g. disk drives. The host data processing system issues data transfer commands to the subsystem to initiate transfer of data between the host processing system and the device(s) associated with the data storage subsystem. Read/write data is transferred directly from device to host via a buffer controller. For a read operation, the read command from the host data processing system specifies the data to be transferred and the start address in host memory to which the data should be sent. The device controller of the data storage subsystem is capable of respecifying or amending the start address specified by the host in the rad command. This provides a performance bonefit for split data transfers.

Abstract: Described is a network addressing scheme in which a message sent from a source node to a destination node includes a path address which defines the path over which the message should travel to reach the destination node. At each node along the path between the source and destination, the path address is compared against a predetermined value, and on determining that the address and predetermined value are different, the node modifies the address before forwarding the message onto the next node. In a switch node having three or more ports, the identity of the output port is determined from the path address and a portion of the address is deleted before sending the message out on that output port. Also described is a method of configuring a network in which one or more initiator nodes are defined, the initiator nodes issuing query messages to an adjacent node which responds by sending the initiator details of the number of operational ports which are implemented in the adjacent node.

Abstract: Described is a method of error recovery in a data communication system of the kind comprising two nodes connected by a serial link and wherein data is transmitted between the nodes in the form of packets of a predefined format. Each node receives data over an inbound line and transmits data over an outbound line. When an error is detected, both nodes enter a link check state, invoke a Link Error Recovery Procedure (ERP) and exchange status by means of Link Resets. Error recovery is performed separately for each line. Each node is responsible for recovering packets that were lost on its outbound line. In normal operation of the link, the transmitter does not reuse a packet buffer until it has received a response from the connected node indicating that the packet was correctly received. Therefore when an error occurs, the affected packets are still available for retransmission.

Abstract: In order to compensate for image distortion introduced into a digitally-controlled raster-scan CRT by the finite video amplifier rise and fall times, the digital video drive waveform is subject to selective pulse stretching to extend where possible the duration of pels which represent critical features of the image. This is achieved by decoding means for examining each pel at least in relation to its two immediate neighbors on either side in order to detect predetermined relationships between the values of the pels, and retiming means for selectively advancing or delaying the transitions between consecutive pels of different value in accordance with the relationships so detected.