Abstract: A structure and method for forming a split probe pad structure for a semiconductor structure. The split probe pad structure may include a first probe pad structure over a substrate, the first probe pad structure including a first probe pad in electrical communication with the substrate; a second probe pad structure over the substrate, the second probe pad structure including a second probe pad in electrical communication with the substrate, wherein the second probe pad structure is laterally separated from the first probe pad structure; and a non-metal region between the first probe pad structure and the second probe pad structure. The split probe pad structure may be formed in a kerf region of the semiconductor structure. The non-metal region may include a dielectric material.

Abstract: A structure and method for forming a split probe pad structure for a semiconductor structure. The split probe pad structure may include a first probe pad structure over a substrate, the first probe pad structure including a first probe pad in electrical communication with the substrate; a second probe pad structure over the substrate, the second probe pad structure including a second probe pad in electrical communication with the substrate, wherein the second probe pad structure is laterally separated from the first probe pad structure; and a non-metal region between the first probe pad structure and the second probe pad structure. The split probe pad structure may be formed in a kerf region of the semiconductor structure. The non-metal region may include a dielectric material.

Abstract: A method of forming an IC structure, including: forming a first plurality of active devices within a first semiconductor layer over a substrate; forming a first wiring layer over the first semiconductor layer, the first wiring layer including a first metal having a melting point greater than approximately 1400 degrees Celsius (° C.); forming a second semiconductor layer over the first wiring layer; forming a second plurality of active devices within the second semiconductor layer; and forming a second wiring layer over the second semiconductor layer, the second wiring layer including the first metal having a melting point greater than approximately 1400 degrees Celsius (° C.).

Abstract: An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices are positioned on the first side of the single semiconductor substrate, and a second plurality of active devices are positioned on the opposing, second side of the single semiconductor substrate. A TSV may electrically couple active devices on either side. Use of a single semiconductor substrate with active devices on both sides reduces the number of semiconductor layers used and allows annealing without damaging BEOL interconnects during fabrication.

Abstract: An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first wiring layer; and a second wiring layer over the second layer, wherein the first wiring layer and the second wiring layer each including a first metal resistant to high temperature.

Abstract: An integrated circuit (IC) structure including: a first layer including a first plurality of active devices in a first semiconductor layer over a substrate; a first wiring layer over the first layer; a second layer including a second plurality of active devices within a second semiconductor layer over the first wiring layer; and a second wiring layer over the second layer, wherein the first wiring layer and the second wiring layer each including a first metal resistant to high temperature.

Abstract: An integrated circuit (IC) structure uses a single semiconductor substrate having a first side and an opposing, second side. A first plurality of active devices are positioned on the first side of the single semiconductor substrate, and a second plurality of active devices are positioned on the opposing, second side of the single semiconductor substrate. A TSV may electrically couple active devices on either side. Use of a single semiconductor substrate with active devices on both sides reduces the number of semiconductor layers used and allows annealing without damaging BEOL interconnects during fabrication.

Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.

Abstract: A semiconductor product comprises a semiconductor substrate having a top surface and a bottom surface including a semiconductor chip. The semiconductor substrate has a top surface and a perimeter. A barrier is formed in the chip within the perimeter. An Ultra Deep Isolation Trench (UDIT) is cut in the top surface of the chip extending down therein between the perimeter and the barrier. A ILD structure with low-k pSICOH dielectric and hard mask layers is formed over the substrate prior to forming the barrier and the UDIT. The ILD structure interconnection structures can be recessed down to the substrate aside from the UDIT.