Abstract: An apparatus and system, including a switch; and a set of tiles; wherein each of the set of tiles include a PIC die, a DSP die, a driver die, and a TIA die and methods thereto.

Abstract: A method, system, and apparatus for multiplexing comprising feeding a signal into a sampler, splitting a first signal into an even branch at a first set of times, splitting a second signal into an odd branch at a second set of times, feeding a switch bleed current into the first branch at the second set of time and feeding the switch bleed current into the second branch at the first set of time.

Abstract: A CMOS integrated circuit comprising digital-to-analogue converters (DACs), analogue-to-digital converters (ADCs), a digital signal processor (DSP), on-chip switching, an on-chip processor; and logic enabling to receive data from data sources in a 5G network, combine the data from the data sources into a single data stream, encode the single data stream using the DSP, and cause the encoded single data stream to be transmitted to another device in the 5G network.

Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.

Abstract: In a first and second embodiment, an apparatus and system comprising a set of voltage controlled oscillators (VCOs); wherein each VCO of the set of VCOs has an LC tank; wherein each VCO of the set of VCOs is connected via a transmission line. In a third embodiment, a method comprising connecting each VCO in a set of VCOs by connecting each respective LC tank of each VCO of the set of VCOs with a transmission line.

Abstract: An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.

Abstract: An apparatus and system, including a switch; and a set of tiles; wherein each of the set of tiles include a PIC die, a DSP die, a driver die, and a TIA die and methods thereto.

Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.

Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.

Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.