Patents by Inventor Ian Dedic
Ian Dedic has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 12232264Abstract: In an embodiment, an apparatus and system comprising a first inductor with a first diameter; and a switched inductor including a metal layer and a switch; wherein when the switch is closed the switch connects the metal layer of the switched inductor to form an inductor with a parallel circuit enabling current to flow through the switched conductor; and wherein when the switch is open, current is not enabled to flow through the switched conductor. In another embodiment, a method for tuning a high-Q inductor, the method comprising closing a switch of a switched inductor, wherein the switch connects the switched inductor to a first inductor; wherein closing the switch enables current to flow though the switched inductor as well as the first inductor to change the inductance of the high Q inductor.Type: GrantFiled: September 9, 2019Date of Patent: February 18, 2025Assignee: ACACIA COMMUNICATIONS, INC.Inventors: Ian Dedic, David Enright, Darren Walker, Tarun Gupta
-
Patent number: 12184301Abstract: An apparatus, method, and system for converting a charge to a voltage.Type: GrantFiled: July 13, 2021Date of Patent: December 31, 2024Assignee: ACACIA COMMUNICATIONS, INC.Inventors: Ian Dedic, Gavin Allen, Ramesh K. Singh
-
Patent number: 12166501Abstract: A combinational circuit (e.g., multiplexer or demultiplexer) comprises a sub-circuit that comprises first and second current paths from an input of the combinational circuit to an output of the combinational circuit, such that substantially all input current at the input of the combinational circuit is conducted by the sub-circuit via the first and second current paths to the output of the combinational circuit. The first current path comprises a first inductor and a first switch; and the second current path comprises a second inductor and a second switch. The first inductor is part of an output LC transmission line of the sub-circuit; the second inductor is part of an input LC transmission line of the sub-circuit; and the first and second inductors are sized such that parasitic capacitances of the first and second switches are substantially absorbed by the input and output LC transmission lines.Type: GrantFiled: June 23, 2022Date of Patent: December 10, 2024Assignee: CISCO TECHNOLOGY, INC.Inventor: Ian Dedic
-
Patent number: 12130656Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.Type: GrantFiled: June 29, 2023Date of Patent: October 29, 2024Assignee: ACACIA COMMUNICATIONS, INC.Inventors: Gavin Allen, Ian Dedic, Bo Yang, Taran Gupta
-
Patent number: 12107544Abstract: An apparatus comprising two inductors; wherein the two inductors are layered on top of each other in different layers of metal of a circuit; wherein each inductor of the inductor has a set of turns; wherein the current path of the two inductors is in the same direction.Type: GrantFiled: November 15, 2019Date of Patent: October 1, 2024Assignee: ACACIA COMMUNICATIONS, INC.Inventors: Ian Dedic, Gavin Allen, David Enright, Guojun Ren
-
Patent number: 12041397Abstract: An apparatus and system, including a switch; and a set of tiles; wherein each of the set of tiles include a PIC die, a DSP die, a driver die, and a TIA die and methods thereto.Type: GrantFiled: August 26, 2022Date of Patent: July 16, 2024Assignee: Acacia Communications, Inc.Inventors: Christopher Doerr, Benny Mikkelsen, Ian Dedic, John LoMedico, Song Jiang
-
Patent number: 11956019Abstract: A method, system, and apparatus for multiplexing comprising feeding a signal into a sampler, splitting a first signal into an even branch at a first set of times, splitting a second signal into an odd branch at a second set of times, feeding a switch bleed current into the first branch at the second set of time and feeding the switch bleed current into the second branch at the first set of time.Type: GrantFiled: February 19, 2021Date of Patent: April 9, 2024Assignee: Acacia Communications, Inc.Inventors: Ramesh K. Singh, Ian Dedic, Gavin Allen
-
Patent number: 11923910Abstract: A CMOS integrated circuit comprising digital-to-analogue converters (DACs), analogue-to-digital converters (ADCs), a digital signal processor (DSP), on-chip switching, an on-chip processor; and logic enabling to receive data from data sources in a 5G network, combine the data from the data sources into a single data stream, encode the single data stream using the DSP, and cause the encoded single data stream to be transmitted to another device in the 5G network.Type: GrantFiled: November 20, 2021Date of Patent: March 5, 2024Assignee: Acacia Communications, Inc.Inventors: Christian Rasmussen, Ian Dedic, Benny Mikkelsen
-
Patent number: 11698658Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.Type: GrantFiled: June 6, 2022Date of Patent: July 11, 2023Assignee: Acacia Communications, Inc.Inventors: Gavin Allen, Ian Dedic, Bo Yang, Tarun Gupta
-
Patent number: 11599140Abstract: In a first and second embodiment, an apparatus and system comprising a set of voltage controlled oscillators (VCOs); wherein each VCO of the set of VCOs has an LC tank; wherein each VCO of the set of VCOs is connected via a transmission line. In a third embodiment, a method comprising connecting each VCO in a set of VCOs by connecting each respective LC tank of each VCO of the set of VCOs with a transmission line.Type: GrantFiled: September 30, 2019Date of Patent: March 7, 2023Assignee: Acacia Communications, Inc.Inventors: Ian Dedic, David Enright, Tarun Gupta
-
Patent number: 11543850Abstract: An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.Type: GrantFiled: January 31, 2020Date of Patent: January 3, 2023Assignee: Acacia Communications, Inc.Inventors: Ian Dedic, Gavin Allen, David Enright, Bo Yang, Tarun Gupta
-
Patent number: 11432056Abstract: An apparatus and system, including a switch; and a set of tiles; wherein each of the set of tiles include a PIC die, a DSP die, a driver die, and a TIA die and methods thereto.Type: GrantFiled: July 24, 2020Date of Patent: August 30, 2022Assignee: Acacia Communications, Inc.Inventors: Christopher Doerr, Benny Mikkelsen, Ian Dedic, John LoMedico, Song Jiang
-
Patent number: 6288665Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.Type: GrantFiled: May 9, 2000Date of Patent: September 11, 2001Assignee: Fujitsu LimitedInventors: Sanroku Tsukamoto, Ian Dedic, Kuniyoshi Kamei, Toshiaki Endo, Masaru Sawada, Hiroko Murakami
-
Patent number: 6288668Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.Type: GrantFiled: February 21, 1996Date of Patent: September 11, 2001Assignee: Fujitsu LimitedInventors: Sanroku Tsukamoto, Ian Dedic, Kuniyoshi Kamei, Toshiaki Endo, Masaru Sawada, Hiroko Murakami
-
Patent number: 6046694Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.Type: GrantFiled: February 21, 1996Date of Patent: April 4, 2000Assignee: Fujitsu LimitedInventors: Sanroku Tsukamoto, Ian Dedic, Kuniyoshi Kamei, Toshiaki Endo, Masaru Sawada, Hiroko Murakami