Abstract: In one embodiment, the disclosure relates to a method of adjusting a current steering multiplexer. The method includes providing a first subDAC comprising a first current mode output; providing a second subDAC comprising a second current mode output; and providing a current mode multiplexer. The method may also include clocking the current mode multiplexer using a first clock signal having a first frequency; clocking the first subDAC using a second clock signal having a second frequency; clocking the second subDAC using the second clock signal, wherein the second frequency is twice the first frequency; and combining currents from the first current mode output and the second current mode output.

Abstract: In one embodiment, the disclosure relates to a current steering DAC system. The system may include a current steering digital to analogy converter (DAC) that includes a clock buffer configured to generate a first clock signal having a first frequency and a second clock signal having a second frequency; a tail node; a first clock switch in electrical communication with the tail node; a second clock switch in electrical communication with the tail node; and a current source comprising an inductor having an inductance, the current source in electrical communication with the tail node.

Abstract: In one embodiment, the disclosure relates to a phase detector. The phase detector may include a first inductor having an inductance L1; a second inductor having an inductance L2; and a frequency mixer having a parasitic capacitance CTail, the frequency mixer comprising, a common node tail; a first clock signal generator configured to output a first clock signal having a first frequency, a second clock signal generator configured to output a second clock signal having a second frequency, the first clock signal generator and the second clock signal generator in electrical communication with the common node tail, a first resistor in electrical communication with the first clock signal generator, a second resistor in electrical communication with the second clock signal generator, and an output channel configured to transmit a DC voltage signal (Vphase) that corresponds to the phase relationship between the first clock signal and the second clock signal.

Abstract: A method, system, and apparatus for multiplexing comprising feeding a signal into a sampler, splitting a first signal into an even branch at a first set of times, splitting a second signal into an odd branch at a second set of times, feeding a switch bleed current into the first branch at the second set of time and feeding the switch bleed current into the second branch at the first set of time.

Abstract: In an embodiment, an apparatus and system comprising a first inductor with a first diameter; and a switched inductor including a metal layer and a switch; wherein when the switch is closed the switch connects the metal layer of the switched inductor to form an inductor with a parallel circuit enabling current to flow through the switched conductor; and wherein when the switch is open, current is not enabled to flow through the switched conductor. In another embodiment, a method for tuning a high-Q inductor, the method comprising closing a switch of a switched inductor, wherein the switch connects the switched inductor to a first inductor; wherein closing the switch enables current to flow though the switched inductor as well as the first inductor to change the inductance of the high Q inductor.

Abstract: An apparatus, method, and system for converting a charge to a voltage.

Abstract: A combinational circuit (e.g., multiplexer or demultiplexer) comprises a sub-circuit that comprises first and second current paths from an input of the combinational circuit to an output of the combinational circuit, such that substantially all input current at the input of the combinational circuit is conducted by the sub-circuit via the first and second current paths to the output of the combinational circuit. The first current path comprises a first inductor and a first switch; and the second current path comprises a second inductor and a second switch. The first inductor is part of an output LC transmission line of the sub-circuit; the second inductor is part of an input LC transmission line of the sub-circuit; and the first and second inductors are sized such that parasitic capacitances of the first and second switches are substantially absorbed by the input and output LC transmission lines.

Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.

Abstract: An apparatus comprising two inductors; wherein the two inductors are layered on top of each other in different layers of metal of a circuit; wherein each inductor of the inductor has a set of turns; wherein the current path of the two inductors is in the same direction.

Abstract: An apparatus and system, including a switch; and a set of tiles; wherein each of the set of tiles include a PIC die, a DSP die, a driver die, and a TIA die and methods thereto.

Abstract: A method, system, and apparatus for multiplexing comprising feeding a signal into a sampler, splitting a first signal into an even branch at a first set of times, splitting a second signal into an odd branch at a second set of times, feeding a switch bleed current into the first branch at the second set of time and feeding the switch bleed current into the second branch at the first set of time.

Abstract: A CMOS integrated circuit comprising digital-to-analogue converters (DACs), analogue-to-digital converters (ADCs), a digital signal processor (DSP), on-chip switching, an on-chip processor; and logic enabling to receive data from data sources in a 5G network, combine the data from the data sources into a single data stream, encode the single data stream using the DSP, and cause the encoded single data stream to be transmitted to another device in the 5G network.

Abstract: A method system, and apparatus for adjusting skew in a circuit comprising feeding an input clock into a first push-pull source follower stage, feeding an inverse of an input clock bar into a first CMOS inverter stage, creating an output clock based on an equal contribution of the input clock of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage, feeding the input clock bar into a first push-pull source follower stage, feeding an inverse of the input clock into a first CMOS inverter stage, and creating an output clock based on an equal contribution of the input clock bar of the first push-pull follower stage and the inverse of the input clock bar of the first CMOS invert stage.

Abstract: In a first and second embodiment, an apparatus and system comprising a set of voltage controlled oscillators (VCOs); wherein each VCO of the set of VCOs has an LC tank; wherein each VCO of the set of VCOs is connected via a transmission line. In a third embodiment, a method comprising connecting each VCO in a set of VCOs by connecting each respective LC tank of each VCO of the set of VCOs with a transmission line.

Abstract: An apparatus and system for a clock buffer. The clock buffer comprises a source follower, and the source follower comprises a voltage source and a resistor.

Abstract: An apparatus and system, including a switch; and a set of tiles; wherein each of the set of tiles include a PIC die, a DSP die, a driver die, and a TIA die and methods thereto.

Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.

Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.

Abstract: An encoder for an A/D converter includes a plurality of ROM cells connected between bit lines and word lines. Each of the ROM cells is responsive to a word line select signal supplied to a word line associated with each of the ROM cells for supplying a digital output signal according to the word line select signal to a bit line associated with each of the ROM cells. A logic processor is coupled to one of the bit lines and to two of the word lines used to select a ROM cell connected to the bit line. The logic processor produces an output signal indicative of a selection of the ROM cell connected to the bit line, based on word line select signals supplied on the two word lines.