Abstract: The present disclosure relates to scalable network security functions and handling of packet flows between network security zones in a communications network. Packets that are part of a bidirectional packet flow between the network security zones are received, and a determination is made as to an instance of a security application to which to assign the bidirectional packet flow for security processing. The determination is made based on relative loading of a plurality of identical instances of the security application running on a host machine. All of the received packets that are part of the bidirectional packet flow are directed for processing on the host machine by the one of the security application instances.

Abstract: The present disclosure relates to scalable network security functions and handling of packet flows between network security zones in a communications network. Packets that are part of a bidirectional packet flow between the network security zones are received, and a determination is made as to an instance of a security application to which to assign the bidirectional packet flow for security processing. The determination is made based on relative loading of a plurality of identical instances of the security application running on a host machine. All of the received packets that are part of the bidirectional packet flow are directed for processing on the host machine by the one of the security application instances.

Abstract: The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost).

Abstract: A time-space switch in a ring architecture includes input circuitry including N links each receiving M timeslots, a two-dimensional matrix of a plurality of switching circuits, the two-dimensional matrix is configured to receive from the input circuitry each of the M timeslots from the N links in a pipelined manner, and output circuitry including N links configured to receive any of the M timeslots from any of the N links from the two-dimensional matrix. The input circuitry, the two-dimensional matrix, and the output circuitry are arranged in a ring architecture therebetween. A link encoding protocol method performed in electrical circuitry includes receiving a plurality of time slots, grouping the plurality of time slots into time slot groups, performing a cyclic redundancy check between adjacent time slot groups, 64/65B encoding the time slot groups, and forward error correction encoding a plurality of 65B codewords from the 64/65B encoding.

Abstract: The present disclosure provides a structured, pipelined large time-space switch and method of operation resolving interconnect complexity. The time-space switch results in an interconnect complexity that does not grow as the spatial dimension is increased and results in a reduction of long high fan-out nets, a quicker layout, and improved clock speed. With respect to time-space switch fabric implementation, the present invention improves the maximum clock frequency of the switch fabric, and improves integrated circuit layout time by eliminating long high fan-out nets. Certain high-speed large switch fabrics may not be realizable without this implementation, and it significantly reduces implementation time (and cost).

Abstract: A system and method for canceling interference over a group of signals. One or more wires in a group of wires are designated to carry one or more reference signals. The one or more reference signals are used to cancel interference from the data carrying signals in the group of signals. Preferably, the one or more reference signals are subtracted from the data carrying signals to cancel interference from the data carrying signals. Analog or digital elements can be used to subtract the one or more reference signals from the data carrying signals. For example, an operation amplifier or a DSP may be used to perform the subtraction. Filters may be used to further adapt the one or more reference signals prior to the subtracting step to optimize interference cancellation. The filters may be either digital or analog.

Abstract: A system and method for optimizing the transmission of signals over a group of wires. In a preferred form of the present invention, a multi-wire bus connects a common card to a plurality of line cards. A framing protocol controls transmissions between the common card and the plurality of line cards. The framing protocol includes a frame having a prefix that identifies in which direction a given transmission will occur. The prefix also identifies over which wire or wires a given line card will receive data. Each of the line cards are configured to interpret the prefix so that at any given time data can be transmitted from the common card to one or more of the line cards by either transmission over a single wire or a plurality of wires.

Abstract: A system and method for optimizing the transmission of signals over a group of wires. In a preferred form of the present invention, a multi-wire bus connects a common card to a plurality of line cards. A framing protocol controls transmissions between the common card and the plurality of line cards. The framing protocol includes a frame having a prefix that identifies in which direction a given transmission will occur. The prefix also identifies over which wire or wires a given line card will receive data. Each of the line cards are configured to interpret the prefix so that at any given time data can be transmitted from the common card to one or more of the line cards by either transmission over a single wire or a plurality of wires.

Abstract: A system and method for canceling interference over a group of signals. One or more wires in a group of wires are designated to carry one or more reference signals. The one or more reference signals are used to cancel interference from the data carrying signals in the group of signals. Preferably, the one or more reference signals are subtracted from the data carrying signals to cancel interference from the data carrying signals. Analog or digital elements can be used to subtract the one or more reference signals from the data carrying signals. For example, an operation amplifier or a DSP may be used to perform the subtraction. Filters may be used to further adapt the one or more reference signals prior to the subtracting step to optimize interference cancellation. The filters may be either digital or analog.

Abstract: A blind convergence process for an adaptive decision feedback equalizer that includes an quadrature amplitude modulation (QAM) slicer having a index n, a forward filter defined by a plurality of forward tap coefficients and a feedback filter defined by a plurality of feedback tap coefficients. The blind convergence process includes initializing the forward tap coefficients of the forward filter and the feedback tap coefficients of the feedback filters with predetermined values. The slicer operates in two modes: a clustering mode and a decision directed mode. In the clustering mode the following steps are performed: (1) update the forward tap coefficients of the forward filter using an error estimate (e.g. Sato error), and (2) update the feedback tap coefficients of the feedback filter using an error estimate (e.g. Sato error).

Abstract: An automatic gain control method and apparatus for modem receivers. The automatic gain control circuit includes a programmable loop gain for scaling a digital signal Y to a first prescribed level during a first mode of operation and to a second prescribed level during a second mode of operation; and filters and converters for converting the scaled signal Y into an analog gain control signal for input to the analog AGC. The gain control circuit and method of operation provides control over the parameters of the programmable loop gain such that during start-up initialization the signal Y is scaled to the first prescribed value and during steady state operation the signal Y is scaled to the second prescribed value. This is accomplished by changing the gain parameter of the programmable loop gain.

Abstract: A method and apparatus for timing recovery in modem receivers. The timing recovery circuit includes a voltage controlled oscillator for controlling the voltage controlled sampling frequency of an analog-to-digital converter. The oscillator generates a timing clock that is dependent on an average phase error signal calculated from Nyquist signals of the input signal. A phase detector circuit is used for generating an instantaneous phase error signal of the in-phase and quadrature-phase signals. A digital loop filter receives the instantaneous phase error signal over time to generate the average phase error signal. The average phase error signal is conditioned further (after conversion to analog) by an analog loop filter such that the average phase error signal adjusts the timing clock generated by the oscillator. The low pass filter provides control of the acquisition and steady state operations by changing the gain and pole parameters of the filter.

Abstract: A method of timing recovery convergence monitoring in modems using an average phase error signal. The method involves continuously tracking the peak of the average phase error. The average phase error is compared to a dynamic threshold (i.e. a threshold that can change over time based on changes to the detected peak at a given time). Convergence is declared when the average phase error remains less than the threshold over a given length of time (i.e. after processing a prescribed number of consecutive samples).

Abstract: A method of detecting misconvergence in an equalizer having a quadrature amplitude modulation (QAM) slicer having an index n. The method includes the steps of initializing a plurality of signal counters then processing random symbols (for example between 500 and 20000 symbols) through the equalizer where the symbols are quantized into an appropriate constellation point in an n-QAM constellation map, where each signal counter corresponds to a respective one of the constellation points in the constellation map. The signal counters are incremented when one of the symbols is quantized to the corresponding constellation point. After the signals have been processed into the constellation map the number of non-zero counters are detected. If the number of non-zero counters is less than a prescribed number (for example between approximately 0.5n and approximately 0.

Abstract: A method of estimating signal-to-noise ratio at an output of an adaptive decision feedback equalizer receiving an input signal. The method of SNR estimation includes (a) calculating an average output error of the equalizer; and (b) estimating the signal-to-noise ratio (SNRest=kn−20 log10(Eavg)) where kn is a constant based on a QAM index n and Eavg is the average output error of the equalizer. The estimated SNR can be used to detect proper equalizer convergence by comparing the estimated SNR to an SNR threshold (e.g. lowest SNR for a 4QAM signal), wherein the equalizer is not properly converged when the estimated SNR is lower than the SNR threshold. The estimated SNR can also be used to adjust the operating QAM index of the equalizer by comparing the estimated SNR to an ideal SNR based on an objective bit error rate for a prescribed QAM index, and reconverging the equalizer at a QAM index lower than the prescribed QAM index when the estimated SNR is lower than the ideal SNR.

Abstract: A blind convergence process for an adaptive decision feedback equalizer having an quadrature amplitude modulation (QAM) slicer, a forward filter defined by a plurality of forward tap coefficients and a feedback filter defined by a plurality of feedback tap coefficients. The blind convergence process includes the step of initializing the forward tap coefficients of the forward filter and the feedback tap coefficients of the feedback filters with predetermined values. The QAM slicer operates in two modes: a clustering mode and a decision directed mode. The clustering mode includes the step of updating only the forward tap coefficients of the forward filter for a prescribed start-up QAM index (such a 4 QAM). The decision directed mode is predefined for set of QAM indexes having values n1, n2, . . .

Abstract: A method of reducing leakage noise introduced to an equalizer in a modem during steady state operation. The equalizer includes forward and feedback filters represented by tap coefficients. The tap coefficients of the filters are updated using least mean squares adaptation equations at a symbol rate during steady state operation. The method of the invention includes the steps of: (a) reducing the absolute value of the updated tap coefficients of the filters at a prescribed rate that is less than the symbol rate. Long term convergence stability is improved and leakage noise is reduced by leaking the filter coefficients less frequently than the symbol rate.