Abstract: A system and method are disclosed for generating a transition in a laser control signal at a precise point in time. A write strategy processor is configured to input a sequence of data and to determine a transition in a laser control signal from the sequence of data. The transition is specified by a number of pulse clock units and a delay. A write pulse generator is configured to input the number of pulse clock units and the delay and to generate a transition by creating a signal having a transition at the time specified by the number of pulse clock units and delaying the transition by the specified delay.

Abstract: A system and method are disclosed for generating a transition in a laser control signal at a precise point in time. A write strategy processor is configured to input a sequence of data and to determine a transition in a laser control signal from the sequence of data. The transition is specified by a number of pulse clock units and a delay. A write pulse generator is configured to input the number of pulse clock units and the delay and to generate a transition by creating a signal having a transition at the time specified by the number of pulse clock units and delaying the transition by the specified delay.

Abstract: A programmable speed/logic arrangement for integrated devices having logic matrices which permits a user to determine the method by which the a logic matrix of an integrated circuit is switched between a low power standby and a high power operation mode. The arrangement includes a switching circuit for switching the logic matrix between modes, switch operating circuit responsive to at least one of internal and external wake-up pulses for operating the switching circuit, and an internal pulse generator for selectively generating a wake-up pulse internally of the matrix. The logic matrix is provided with a specific addressable location which is responsive to an appropriate address to generate the internal wake-up pulse as well as a dedicated input responsive to an externally generated wake-up pulse. Further, high/low power fuses or E/EE CMOS devices can be employed to programmably connect the logic matrix to different levels of high power sources.

Abstract: A high reliability, low power fuse programmable DC level generator is implemented by providing at least one fuse in each branch of a resistive bridge such that programming of the level generator results in providing a blown fuse in the current path and as a consequence results in low current and low power under all operating conditions.

Abstract: A programmable logic circuit comprises a Programmable Array Logic (PAL) circuit in which individual product terms may be shared simultaneously by one or more of the circuit outputs. The product terms are selectively connected to the circuit outputs by programmable elements (such as a fusible link) to increase design flexibility. Isolating devices are provided in series with the programmable elements to allow for the simultaneous product term sharing.