Patents by Inventor Ian Harvey Arellano

Ian Harvey Arellano has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11929259
    Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.
    Type: Grant
    Filed: June 21, 2021
    Date of Patent: March 12, 2024
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Ian Harvey Arellano, Aaron Cadag, Ela Mia Cadag
  • Patent number: 11862579
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Grant
    Filed: June 21, 2022
    Date of Patent: January 2, 2024
    Assignee: STMicroelectronics, Inc.
    Inventor: Ian Harvey Arellano
  • Publication number: 20220320014
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Application
    Filed: June 21, 2022
    Publication date: October 6, 2022
    Applicant: STMICROELECTRONICS, INC.
    Inventor: Ian Harvey ARELLANO
  • Patent number: 11393774
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Grant
    Filed: August 18, 2020
    Date of Patent: July 19, 2022
    Assignee: STMicroelectronics, Inc.
    Inventor: Ian Harvey Arellano
  • Publication number: 20210313255
    Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Applicant: STMICROELECTRONICS, INC.
    Inventors: Ian Harvey ARELLANO, Aaron CADAG, Ela Mia CADAG
  • Patent number: 11069601
    Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.
    Type: Grant
    Filed: February 1, 2019
    Date of Patent: July 20, 2021
    Assignee: STMicroelectronics, Inc.
    Inventors: Ian Harvey Arellano, Aaron Cadag, Ela Mia Cadag
  • Publication number: 20210057355
    Abstract: In various embodiments, the present disclosure provides semiconductor devices, packages, and methods. In one embodiment, a device includes a die pad, a lead that is spaced apart from the die pad, and an encapsulant on the die pad and the lead. A plurality of cavities extends into at least one of the die pad or the lead to a depth from a surface of the at least one of the die pad or the lead. The depth is within a range from 0.5 ?m to 5 ?m. The encapsulant extends into the plurality of cavities. The cavities facilitate improved adhesion between the die pad or lead and the encapsulant, as the cavities increase a surface area of contact with the encapsulant, and further increase a mechanical interlock with the encapsulant, as the cavities may have a rounded or semi-spherical shape.
    Type: Application
    Filed: August 18, 2020
    Publication date: February 25, 2021
    Inventor: Ian Harvey ARELLANO
  • Patent number: 10461019
    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.
    Type: Grant
    Filed: September 20, 2018
    Date of Patent: October 29, 2019
    Assignee: STMICROELECTRONICS, INC.
    Inventors: Aaron Cadag, Ian Harvey Arellano, Ela Mia Cadag
  • Publication number: 20190267311
    Abstract: The present disclosure is directed to leadless semiconductor packages with improved wettable flanks that encourage the formation of solder fillets when the leadless semiconductor package is mounted to a substrate. The solder fillets are consistently formed and are easily detectable by inspection systems, such as automated optical inspection (AOI) systems.
    Type: Application
    Filed: February 1, 2019
    Publication date: August 29, 2019
    Inventors: Ian Harvey ARELLANO, Aaron CADAG, Ela Mia CADAG
  • Publication number: 20190019745
    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.
    Type: Application
    Filed: September 20, 2018
    Publication date: January 17, 2019
    Inventors: Aaron Cadag, Ian Harvey Arellano, Ela Mia Cadag
  • Publication number: 20180331020
    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.
    Type: Application
    Filed: May 12, 2017
    Publication date: November 15, 2018
    Inventors: Aaron CADAG, Ian Harvey ARELLANO, Ela Mia CADAG
  • Patent number: 10128169
    Abstract: A semiconductor package formed utilizing a removable backside protective layer includes a leadframe, a die pad, leads and a molding compound around them. The first surface of the die pad and leads are exposed to an external environment by the plurality of recesses. The recesses are formed by coupling a removable backside protective layer to the leadframe before applying the molding compound. After the molding compound is applied and cured, the backside protective layer is removed to expose the first surface of the die pad and the first surfaces of the leads so the semiconductor package may be mounted within an electronic device. The removable backside protective layer protects the die pad and the leads from mold flashing and residue when forming the semiconductor package during the fabrication process.
    Type: Grant
    Filed: May 12, 2017
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics, Inc.
    Inventors: Aaron Cadag, Ian Harvey Arellano, Ela Mia Cadag