Abstract: Various implementations of a digital signal processing (DSP) block architecture of a programmable logic device (PLD) and related methods are provided. In one example, a PLD includes a dedicated DSP block. The DSP block includes a first multiplier adapted to multiply a first plurality of input signals to provide a first plurality of product signals. The DSP block also includes a second multiplier adapted to multiply a second plurality of input signals to provide a second plurality of product signals. The DSP block further includes an arithmetic logic unit (ALU) adapted to operate on the first product signals and the second product signals received at first and second operand inputs, respectively, of the ALU to provide a plurality of output signals.

Abstract: Systems and methods are disclosed herein to provide improved alignment of output signals of an analog-to-digital converter (ADC). For example, in accordance with an embodiment of the present invention, a method of aligning digital signals appearing on signal paths of a parallel data bus includes sampling the digital signals at a plurality of delay times to obtain a plurality of sample sets, wherein each sample set is associated with a corresponding delay time. A second digital signal that is misaligned with respect to a first digital signal is identified from the sample sets. The delay time required to align the second digital signal with the first digital signal is determined. The delay of the second digital signal is adjusted by the determined delay time.