Patents by Inventor Ian King
Ian King has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250097323Abstract: In various embodiments, a messaging system is provided, where message streaming is employed to exchange information among various components in a network to facilitate Zero Touch Provisioning (ZTP hereinafter). In those embodiments, messages may pass through the messaging system via REST API or Kafka with consistent message schemas across the messaging system. In various embodiments, message adaptors are provided when different message schemas of the same message is used in the network.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Inventors: Orlando Cuavas, Prakash Srinivasan, Velmurugan Manoharan, Ian King, Nathan Sones
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Patent number: 12243119Abstract: A graphics processor including geometry and fragment processing logic, and a memory manager arranged to allocate and deallocate memory for use to hold tile data. The memory manager tracks which memory regions are allocated to hold tile data of which subdivisions (e.g. macrotiles) of the render area. Once the fragment processing logic has finished processing the tile data of a subdivision, it sends an identifier of that subdivision to the memory manager for deallocation. The processor further comprises a blocking circuit enabling the fragment processing logic to start processing tile data of a second task while the memory manager is still deallocating some of the memory regions allocated to the subdivisions of a first task; by preventing identifiers of subdivisions of the second task being passed to the memory manager until it has completed deallocating the memory regions allocated to the first task.Type: GrantFiled: September 28, 2022Date of Patent: March 4, 2025Assignee: Imagination Technologies LimitedInventors: Michael John Livesley, Ian King, Alistair Goudie
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Publication number: 20250060890Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.Type: ApplicationFiled: November 4, 2024Publication date: February 20, 2025Inventor: Ian King
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Publication number: 20240427632Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.Type: ApplicationFiled: September 6, 2024Publication date: December 26, 2024Inventors: Michael John Livesley, Ian King, Alistair Goudie
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Patent number: 12135886Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.Type: GrantFiled: October 16, 2023Date of Patent: November 5, 2024Assignee: Imagination Technologies LimitedInventor: Ian King
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Publication number: 20240345888Abstract: A method of managing task dependencies within a task queue of a GPU determines a class ID and a resource ID for a task and also for any parent task of the task and outputting the class IDs and resource IDs for both the task itself and any parent task of the task for storage associated with the task in a task queue. The class ID identifies a class of the task from a hierarchy of task classes and the resource ID of the task identifies resources allocated and/or written to by the task.Type: ApplicationFiled: March 29, 2024Publication date: October 17, 2024Inventor: Ian King
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Publication number: 20240345959Abstract: A method of managing shared register allocations in a GPU includes, in response to receiving an allocating task, searching a shared register allocation cache for a cache entry with a cache index that identifies a secondary program that is associated with the allocating task. In response to identifying a cache entry with a cache index that identifies the secondary program that is associated with the allocating task, the method returns an identifier of the cache entry and status information indicating a cache hit. Returning the identifier of the cache entry causes the identifier of the cache entry to be associated with the allocating task and returning the status information indicating a cache hit causes the allocating task not to be issued.Type: ApplicationFiled: March 29, 2024Publication date: October 17, 2024Inventor: Ian King
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Patent number: 12112197Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.Type: GrantFiled: September 27, 2022Date of Patent: October 8, 2024Assignee: Imagination Technologies LimitedInventors: Michael John Livesley, Ian King, Alistair Goudie
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Publication number: 20240303912Abstract: Implementations of post-tessellation blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.Type: ApplicationFiled: May 20, 2024Publication date: September 12, 2024Inventors: Peter Malcolm Lacey, Simon Fenney, Tobias Hector, Ian King
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Publication number: 20240282043Abstract: A method and system for performing safety-critical rendering of a frame in a tile based graphics processing system. Geometry data for the frame is received, including data defining a plurality of primitives representing a plurality of objects in the frame. A definition of a region in the frame is received, the region being associated with one or more primitives among the plurality of primitives. Verification data is received that associates one or more primitives with the region in the frame. The frame is rendered using the geometry data and the rendering of the frame is controlled using the verification data, so that the rendering excludes, from the frame outside the region, the primitives identified by the verification data.Type: ApplicationFiled: April 5, 2024Publication date: August 22, 2024Inventors: Jamie Broome, Ian King
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Publication number: 20240220353Abstract: A method of processing an input task in a processing system involves duplicating the input task so as to form a first task and a second task; allocating memory including a first block of memory configured to store read-write data to be accessed during the processing of the first task; a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task; and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task; and processing the first task and the second task at processing logic of the processing system so as to, respectively, generate first and second outputs.Type: ApplicationFiled: March 18, 2024Publication date: July 4, 2024Inventors: Ian King, Donald Scorgie
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Patent number: 12026828Abstract: Implementations of blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.Type: GrantFiled: May 13, 2022Date of Patent: July 2, 2024Assignee: Imagination Technologies LimitedInventors: Peter Malcolm Lacey, Simon Fenney, Tobias Hector, Ian King
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Patent number: 12004558Abstract: A method of, and equipment for gathering fibres entrained a gas stream, for example by melt blowing, comprises an enclosure having an inlet, through which a gas stream carrying entrained fibres may be directed into the enclosure, a fibre outlet from which an assembly of gathered fibres may be withdrawn from the enclosure and an exhaust outlet through which gas may pass out of the enclosure. The enclosure is constructed to provide a pathway for the fibres from the inlet to the fibre outlet in which surplus gas in the gas stream is separated from the entrained fibres and directed to the exhaust outlet, thereby reducing turbulence in the fibres in the enclosure which may affect the quality of the finished assembly.Type: GrantFiled: February 1, 2022Date of Patent: June 11, 2024Assignees: BRITISH AMERICAN TOBACCO (INVESTMENTS) LIMITED, TOBACCO RESEARCH AND DEVELOPMENT INSTITUTE (PROPRIETARY) LIMITEDInventors: Gary Fallon, John Richardson, Ian King, Gerhard Malin Le Roux, Arnold Leslie Herholdt
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Publication number: 20240185376Abstract: A multicore graphics processing unit (GPU) and a method of operating a GPU are provided. The GPU comprises at least a first core and a second core. At least one of the cores in the multicore GPU comprises a master unit configured to distribute geometry processing tasks between at least the first core and the second core.Type: ApplicationFiled: February 12, 2024Publication date: June 6, 2024Inventor: Ian King
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Publication number: 20240160571Abstract: A processor and a method of obtaining data for a processor are provided. The processor comprises at least a first core, a second core, and a distributed cache. The distributed cache comprises a first cache slice connected to the first core and a second cache slice connected to the second core and to the first cache slice. The first cache slice is configured to receive a memory access request from the first core and forward the memory access request to the second cache slice.Type: ApplicationFiled: September 29, 2023Publication date: May 16, 2024Inventors: Mark Landers, Ian King, Alistair Goudie, Michael John Livesley
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Patent number: 11954784Abstract: A method and system for performing safety-critical rendering of a frame in a tile based graphics processing system. Geometry data for the frame is received, including data defining a plurality of primitives representing a plurality of objects in the frame. A definition of a region in the frame is received, the region being associated with one or more primitives among the plurality of primitives. Verification data is received that associates one or more primitives with the region in the frame. The frame is rendered using the geometry data and the rendering of the frame is controlled using the verification data, so that the rendering excludes, from the frame outside the region, the primitives identified by the verification data.Type: GrantFiled: January 26, 2022Date of Patent: April 9, 2024Assignee: Imagination Technologies LimitedInventors: Jamie Broome, Ian King
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Patent number: 11934257Abstract: A method of processing an input task in a processing system involves duplicating the input task so as to form a first task and a second task; allocating memory including a first block of memory configured to store read-write data to be accessed during the processing of the first task; a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task; and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task; and processing the first task and the second task at processing logic of the processing system so as to, respectively, generate first and second outputs.Type: GrantFiled: December 10, 2021Date of Patent: March 19, 2024Assignee: Imagination Technologies LimitedInventors: Ian King, Donald Scorgie
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Patent number: 11915358Abstract: A method and system for performing safety-critical rendering of a frame in a tile based graphics processing system. Geometry data for the frame is received, including data defining a plurality of primitives representing a plurality of objects in the frame. A definition of a region in the frame is received, the region being associated with one or more primitives among the plurality of primitives. Verification data is received that associates one or more primitives with the region in the frame. The frame is rendered using the geometry data and the rendering of the frame is controlled using the verification data, so that the rendering excludes, from the frame outside the region, the primitives identified by the verification data.Type: GrantFiled: January 26, 2022Date of Patent: February 27, 2024Assignee: Imagination Technologies LimitedInventors: Jamie Broome, Ian King
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Patent number: 11900503Abstract: A multicore graphics processing unit (GPU) and a method of operating a GPU are provided. The GPU comprises at least a first core and a second core. At least one of the cores in the multicore GPU comprises a master unit configured to distribute geometry processing tasks between at least the first core and the second core.Type: GrantFiled: March 24, 2023Date of Patent: February 13, 2024Assignee: Imagination Technologies LimitedInventor: Ian King
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Publication number: 20240045603Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.Type: ApplicationFiled: October 16, 2023Publication date: February 8, 2024Inventor: Ian King