Abstract: A graphics processing system for performing tile-based rendering of a scene that includes safety-critical elements. A geometry engine identifies protected tiles that include safety-critical elements in a geometry processing phase. A fragment processing engine processes each of the protected tiles first and second times so as to respectively generate first and second fragment-processed outputs in a fragment processing phase. A check unit compares the first and second fragment-processed outputs for each of the protected tiles and raises a fault signal if the first and second fragment-processed outputs do not match.

Abstract: A master unit in a core of a plurality of cores in a graphics processing unit receives a set of image rendering tasks, assigns a first subset of the image rendering tasks to a first core and assigns a second subset of the image rendering tasks to a second core. The master unit transmits the first subset of image rendering tasks to a slave unit of the first core and transmits the second subset of image rendering tasks to a slave unit of the second core. The master unit stores a credit number for each of the first and second cores and adjusts the credit number of the first and second cores by a first amount for each task in the first and second subset of the image rendering tasks. The slave units transmit credit notifications when tasks have been processed and the master unit adjusts the credit numbers when it receives the notifications.

Abstract: A method of processing instructions at a processing unit having a parallel processing engine. During a mission cycle, a first set of mission operand values is processed in accordance with a mission instruction at a first processing instance to generate a first mission output. In parallel, a second set of mission operand values is processed in accordance with the mission instruction at a second processing instance to generate a second mission output. During a test cycle, a first set of test operand values is processed in accordance with a test instruction at the first processing instance to generate a first test output, and in parallel, a second set of test operand values is processed in accordance with the test instruction at the second processing instance to generate a second test output, where the first set of test operand values is the same as the second set of test operand values.

Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.

Abstract: A graphics processing system for performing tile-based rendering of a scene that includes safety-critical elements. The graphics processing system includes a geometry engine configured to, in a geometry processing phase, identify protected tiles that include safety-critical elements; a fragment processing engine configured to, in a fragment processing phase, process each of the protected tiles first and second times so as to, respectively, generate first and second fragment-processed outputs; and a check unit configured to, for each of the protected tiles, compare the first and second fragment-processed outputs and raise a fault signal if the first and second fragment-processed outputs do not match.

Abstract: A processor includes a hardware pipeline comprising fixed-function hardware, a register bank to which software can write task descriptors, and a blocking circuit disposed between an upstream section and a downstream section of the hardware pipeline, wherein the blocking circuit has an open state in which data passes from the upstream section to the downstream section, and a closed state that blocks data passing from the upstream section to the downstream section. Control circuitry triggers the upstream section to start processing a second task while the downstream section is still processing the first task, and switches the blocking circuit to the closed state, in response to detecting that the upstream section has finished processing a first task.

Abstract: A set of image rendering tasks and state information are distributed in a graphics processing unit (GPU) having a plurality of cores. A first master unit in one of the cores receives the set of image rendering tasks and the state information, and stores the state information in a memory. The first master unit splits the set of image rendering tasks into a first subset of tasks and a second subset of tasks, wherein the first subset of tasks is assigned to the first core, and the second subset of tasks is assigned to the second core. At least a first portion of the state information is transmitted to the first core, and at least a second portion of the state information is transmitted to the second core. The first subset of tasks is transmitted to the first core, and the second subset of tasks is transmitted to the second core.

Abstract: A processor includes a blocking circuit between an upstream section and a downstream section of a hardware pipeline, and control circuitry which triggers the upstream section to process an upstream phase of a first task, with the blocking circuit in an open state whereby first data from the processing of the upstream phase of the first task passes through from the upstream section to be processed in a downstream phase of the first task. In response to detecting that the upstream section has finished processing the upstream phase of the first task, the control circuitry triggers the upstream section to start processing a second task while the downstream section is still processing the downstream phase of the first task, and switches the blocking circuit to a closed state blocking second data from the processing of the upstream phase of the second task passing to the downstream section.

Abstract: Implementations of post-tessellation blender hardware perform both domain shading and blending and while some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations. In the event of a cache miss for a UV coordinate of a domain space vertex, a cache outputs the UV coordinate to a domain shader, where the domain space vertex comprises UV coordinates of neighbor vertices that are not inherent from the UV coordinates of the vertex itself.

Abstract: A set of image rendering tasks and state information are distributed in a graphics processing unit (GPU) having a plurality of cores. A first master unit in one of the cores receives the set of image rendering tasks and the state information, and stores the state information in a memory. The first master unit splits the set of image rendering tasks into a first subset of tasks and a second subset of tasks, wherein the first subset of tasks is assigned to the first core, and the second subset of tasks is assigned to the second core. At least a first portion of the state information is transmitted to the first core, and at least a second portion of the state information is transmitted to the second core. The first subset of tasks is transmitted to the first core, and the second subset of tasks is transmitted to the second core.

Abstract: In various embodiments, a messaging system is provided, where message streaming is employed to exchange information among various components in a network to facilitate Zero Touch Provisioning (ZTP hereinafter). In those embodiments, messages may pass through the messaging system via REST API or Kafka with consistent message schemas across the messaging system. In various embodiments, message adaptors are provided when different message schemas of the same message is used in the network.

Abstract: A method of operating a GPU uses input attributes in executing a first part of a geometry task fetched by a shader core. The first part of the task executes a first part of a shader to calculate position data for each instance of the task. The first part of the task is executed to output the position data for each instance of the task. The task is then descheduled until cull results are received for each instance. In response to receiving cull results indicating at least one remaining instance in the task, input attributes used in executing a second part of a task are fetched. The second part of the task executes a second part of a shader to calculate varyings for each remaining instance. The second part of the task is executed and the varyings for each remaining instance are output.

Abstract: A method of managing resources in a GPU comprises allocating a region of off-chip storage to a geometry task on creation of the geometry task and receiving, at an on-chip store in the GPU, a memory allocation request for the geometry task from a shader core in the GPU, wherein the memory allocation request is received after generation of geometry data for the geometry task. In response to receiving the memory allocation request, the method comprises determining, by the on-chip store, whether to allocate a region of the on-chip store to the geometry task. In response to allocating the region of the on-chip store, geometry data for the geometry task is written to the on-chip store and in response to determining not to allocate the region of the on-chip store, the geometry data is written to the allocated region of off-chip storage.

Abstract: A graphics processing system includes a plurality of processing units, wherein the graphics processing system is configured to process a task first and second times at the plurality of processing units. Data identifying which processing unit of the plurality of processing units the task has been allocated to is consulted on allocating the task to a processing unit for processing for a second time, and, in response, the task is allocated for processing for the second time to any processing unit of the plurality of processing units other than the processing unit to which the task was allocated for processing for a first time.

Abstract: A method of processing an input task in a processing system involves duplicating the input task so as to form a first task and a second task; allocating memory including a first block of memory configured to store read-write data to be accessed during the processing of the first task; a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task; and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task; and processing the first task and the second task at processing logic of the processing system so as to, respectively, generate first and second outputs.

Abstract: A processor has first and second cores and a distributed cache that caches a copy of data stored at a plurality of memory addresses of a memory. A first cache slice is connected to the first core, and a second cache slice is connected to the second core. The first cache caches a copy of data stored at a first set of memory addresses, and the second cache slice caches a copy of data stored at a second, different, set of memory addresses.

Abstract: A multicore graphics processing unit (GPU) and a method of operating a GPU are provided. The GPU comprises at least a first core and a second core. At least one of the cores in the multicore GPU comprises a master unit configured to distribute geometry processing tasks between at least the first core and the second core.

Abstract: In various embodiments, a messaging system is provided, where message streaming is employed to exchange information among various components in a network to facilitate Zero Touch Provisioning (ZTP hereinafter). In those embodiments, messages may pass through the messaging system via REST API or Kafka with consistent message schemas across the messaging system. In various embodiments, message adaptors are provided when different message schemas of the same message is used in the network.

Abstract: Implementations of post-tessellation blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.

Abstract: A graphics processing system includes a plurality of processing units, wherein the graphics processing system is configured to process a task first and second times at the plurality of processing units. Data identifying which processing unit of the plurality of processing units the task has been allocated to is consulted on allocating the task to a processing unit for processing for a second time, and, in response, the task is allocated for processing for the second time to any processing unit of the plurality of processing units other than the processing unit to which the task was allocated for processing for a first time.