Patents by Inventor Ian King
Ian King has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250259260Abstract: A multicore graphics processing unit (GPU) and a method of operating a GPU are provided. The GPU comprises at least a first core and a second core. At least one of the cores in the multicore GPU comprises a master unit configured to distribute geometry processing tasks between at least the first core and the second core.Type: ApplicationFiled: April 29, 2025Publication date: August 14, 2025Applicant: Imagination Technologies LimitedInventor: Ian King
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Patent number: 12388914Abstract: In various embodiments, a messaging system is provided, where message streaming is employed to exchange information among various components in a network to facilitate Zero Touch Provisioning (ZTP hereinafter). In those embodiments, messages may pass through the messaging system via REST API or Kafka with consistent message schemas across the messaging system. In various embodiments, message adaptors are provided when different message schemas of the same message is used in the network.Type: GrantFiled: September 15, 2023Date of Patent: August 12, 2025Assignee: DISH WIRELESS L.L.C.Inventors: Orlando Cuavas, Prakash Srinivasan, Velmurugan Manoharan, Ian King, Nathan Sones
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Patent number: 12360864Abstract: A graphics processing system includes a plurality of processing units, wherein the graphics processing system is configured to process a task first and second times at the plurality of processing units. Data identifying which processing unit of the plurality of processing units the task has been allocated to is consulted on allocating the task to a processing unit for processing for a second time, and, in response, the task is allocated for processing for the second time to any processing unit of the plurality of processing units other than the processing unit to which the task was allocated for processing for a first time.Type: GrantFiled: October 6, 2023Date of Patent: July 15, 2025Assignee: Imagination Technologies LimitedInventors: Damien McNamara, Jamie Broome, Ian King, Wei Shao, Mario Sopena Novales, Dilip Bansal
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Publication number: 20250201102Abstract: A method may include receiving a first event notification including a key, received via a first stream of a streaming event platform. The method may include generating a record of the first event notification in a database including a correlation ID and the key. The method may include generating an event indicating an alarm notification, based on the first event notification in a second stream. The method may include receiving a second event notification including the key, received via the first stream. The method may include generating a record of the second event notification in the database including the correlation ID and the key. The method may include determining that the second event notification is related to the first event notification based on the correlation ID and the key. The method may include generating an event indicating an update notification based on the second event notification in the second stream.Type: ApplicationFiled: December 18, 2023Publication date: June 19, 2025Inventor: Ian King
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Patent number: 12326778Abstract: A method of processing an input task in a processing system involves duplicating the input task so as to form a first task and a second task; allocating memory including a first block of memory configured to store read-write data to be accessed during the processing of the first task; a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task; and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task; and processing the first task and the second task at processing logic of the processing system so as to, respectively, generate first and second outputs.Type: GrantFiled: March 18, 2024Date of Patent: June 10, 2025Assignee: Imagination Technologies LimitedInventors: Ian King, Donald Scorgie
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Publication number: 20250182235Abstract: A processor includes a first processing pipeline, a second processing pipeline and a memory management that allocates memory regions from memory for the first processing pipeline to write the data of each of a first of a sequence of tasks, and deallocates each of the memory regions after the data therein has been processed by the second processing pipeline. A blocking circuit enables the second processing pipeline to start processing a second sequence of tasks while the memory management circuit is still deallocating some of the memory regions allocated to the data portions of the first of said sequence of tasks, the blocking circuit preventing identifiers of the data portions of the second task being passed to the memory management circuit until the memory management circuit indicates that it has completed deallocating the memory regions allocated to all the data portions of the first task.Type: ApplicationFiled: January 31, 2025Publication date: June 5, 2025Inventors: Michael John Livesley, Ian King, Alistair Goudie
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Patent number: 12315032Abstract: A multicore graphics processing unit (GPU) and a method of operating a GPU are provided. The GPU comprises at least a first core and a second core. At least one of the cores in the multicore GPU comprises a master unit configured to distribute geometry processing tasks between at least the first core and the second core.Type: GrantFiled: February 12, 2024Date of Patent: May 27, 2025Assignee: Imagination Technologies LimitedInventor: Ian King
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Publication number: 20250165259Abstract: A processing unit configured to perform parallel processing includes a parallel processing engine, the parallel processing engine including a plurality of processing instances configured to process instructions in parallel. Test instruction insertion logic identifies an idle cycle of the parallel processing engine and inserts a test instruction for processing during the idle cycle by each of the plurality of processing instances so as to generate a respective plurality of test outputs. Check logic compares a test output generated during the idle cycle by a first processing instance of the plurality of processing instances with a test output generated during the idle cycle by a second processing instance of the plurality of processing instances, and raises a fault signal if the compared test outputs do not match.Type: ApplicationFiled: October 6, 2024Publication date: May 22, 2025Inventors: Daniel Wilkinson, Ian King
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Patent number: 12299768Abstract: A master unit in a core of a plurality of cores in a graphics processing unit receives a set of image rendering tasks, assigns a first subset of the image rendering tasks to a first core of the plurality of cores and assigns a second subset of the image rendering tasks to a second core of the plurality of cores. The master unit transmits the first subset of image rendering tasks to a slave unit of the first core and transmits the second subset of image rendering tasks to a slave unit of the second core. The master unit stores a credit number for each of the first and second cores and adjusts the credit number of the first and second cores by a first amount for each task in the first and second subset of the image rendering tasks. The slave units transmit credit notifications when tasks have been processed and the master unit adjusts the credit numbers when it receives the notifications.Type: GrantFiled: March 28, 2023Date of Patent: May 13, 2025Assignee: Imagination Technologies LimitedInventors: Michael John Livesley, Ian King
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Publication number: 20250097323Abstract: In various embodiments, a messaging system is provided, where message streaming is employed to exchange information among various components in a network to facilitate Zero Touch Provisioning (ZTP hereinafter). In those embodiments, messages may pass through the messaging system via REST API or Kafka with consistent message schemas across the messaging system. In various embodiments, message adaptors are provided when different message schemas of the same message is used in the network.Type: ApplicationFiled: September 15, 2023Publication date: March 20, 2025Inventors: Orlando Cuavas, Prakash Srinivasan, Velmurugan Manoharan, Ian King, Nathan Sones
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Patent number: 12243119Abstract: A graphics processor including geometry and fragment processing logic, and a memory manager arranged to allocate and deallocate memory for use to hold tile data. The memory manager tracks which memory regions are allocated to hold tile data of which subdivisions (e.g. macrotiles) of the render area. Once the fragment processing logic has finished processing the tile data of a subdivision, it sends an identifier of that subdivision to the memory manager for deallocation. The processor further comprises a blocking circuit enabling the fragment processing logic to start processing tile data of a second task while the memory manager is still deallocating some of the memory regions allocated to the subdivisions of a first task; by preventing identifiers of subdivisions of the second task being passed to the memory manager until it has completed deallocating the memory regions allocated to the first task.Type: GrantFiled: September 28, 2022Date of Patent: March 4, 2025Assignee: Imagination Technologies LimitedInventors: Michael John Livesley, Ian King, Alistair Goudie
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Publication number: 20250060890Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.Type: ApplicationFiled: November 4, 2024Publication date: February 20, 2025Inventor: Ian King
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Publication number: 20240427632Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.Type: ApplicationFiled: September 6, 2024Publication date: December 26, 2024Inventors: Michael John Livesley, Ian King, Alistair Goudie
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Patent number: 12135886Abstract: Methods and storage unit allocators for allocating one or more portions of a storage unit to a plurality of tasks for storing at least two types of data. The method includes receiving a request for one or more portions of the storage unit to store a particular type of data of the at least two types of data for a task of the plurality of tasks; associating the request with one of a plurality of virtual partitionings of the storage unit based on one or more characteristics of the request, each virtual partitioning allotting none, one, or more than one portion of the storage unit to each of the at least two types of data; and allocating the requested one or more portions of the storage unit to the task from the none, one, or more than one portion of the storage unit allotted to the particular type of data in the virtual partitioning associated with the request.Type: GrantFiled: October 16, 2023Date of Patent: November 5, 2024Assignee: Imagination Technologies LimitedInventor: Ian King
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Publication number: 20240345959Abstract: A method of managing shared register allocations in a GPU includes, in response to receiving an allocating task, searching a shared register allocation cache for a cache entry with a cache index that identifies a secondary program that is associated with the allocating task. In response to identifying a cache entry with a cache index that identifies the secondary program that is associated with the allocating task, the method returns an identifier of the cache entry and status information indicating a cache hit. Returning the identifier of the cache entry causes the identifier of the cache entry to be associated with the allocating task and returning the status information indicating a cache hit causes the allocating task not to be issued.Type: ApplicationFiled: March 29, 2024Publication date: October 17, 2024Inventor: Ian King
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Publication number: 20240345888Abstract: A method of managing task dependencies within a task queue of a GPU determines a class ID and a resource ID for a task and also for any parent task of the task and outputting the class IDs and resource IDs for both the task itself and any parent task of the task for storage associated with the task in a task queue. The class ID identifies a class of the task from a hierarchy of task classes and the resource ID of the task identifies resources allocated and/or written to by the task.Type: ApplicationFiled: March 29, 2024Publication date: October 17, 2024Inventor: Ian King
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Patent number: 12112197Abstract: A processor has a register bank to which software writes descriptors specifying tasks to be processed by a hardware pipeline. The register bank includes a plurality of register sets, each for holding the descriptor of a task. The processor includes a first selector operable to connect the execution logic to a selected one of the register sets and thereby enable the software to write successive ones of said descriptors to different ones of said register sets. The processor also includes a second selector operable to connect the hardware pipeline to a selected one of the register sets. The processor further comprises control circuitry configured to control the hardware pipeline to begin processing a current task based on the descriptor in a current one of the register sets while the software is writing the descriptor of another task to another of the register sets.Type: GrantFiled: September 27, 2022Date of Patent: October 8, 2024Assignee: Imagination Technologies LimitedInventors: Michael John Livesley, Ian King, Alistair Goudie
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Publication number: 20240303912Abstract: Implementations of post-tessellation blender hardware perform both domain shading and blending and whilst some vertices may not require blending, all vertices require domain shading. The blender hardware includes a cache and/or a content addressable memory and these data structures are used to reduce duplicate domain shading operations.Type: ApplicationFiled: May 20, 2024Publication date: September 12, 2024Inventors: Peter Malcolm Lacey, Simon Fenney, Tobias Hector, Ian King
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Publication number: 20240282043Abstract: A method and system for performing safety-critical rendering of a frame in a tile based graphics processing system. Geometry data for the frame is received, including data defining a plurality of primitives representing a plurality of objects in the frame. A definition of a region in the frame is received, the region being associated with one or more primitives among the plurality of primitives. Verification data is received that associates one or more primitives with the region in the frame. The frame is rendered using the geometry data and the rendering of the frame is controlled using the verification data, so that the rendering excludes, from the frame outside the region, the primitives identified by the verification data.Type: ApplicationFiled: April 5, 2024Publication date: August 22, 2024Inventors: Jamie Broome, Ian King
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Publication number: 20240220353Abstract: A method of processing an input task in a processing system involves duplicating the input task so as to form a first task and a second task; allocating memory including a first block of memory configured to store read-write data to be accessed during the processing of the first task; a second block of memory configured to store a copy of the read-write data to be accessed during the processing of the second task; and a third block of memory configured to store read-only data to be accessed during the processing of both the first task and the second task; and processing the first task and the second task at processing logic of the processing system so as to, respectively, generate first and second outputs.Type: ApplicationFiled: March 18, 2024Publication date: July 4, 2024Inventors: Ian King, Donald Scorgie