Abstract: A surgery visualization system is described herein. The surgery visualization system includes a display monitor positioned in view of a surgeon and a support arm system including a first support arm and a second support arm. The first and second support arms are orientated such that the display monitor is visible to the surgeon between the first and second support arms. A 3D digital viewport coupled to the first support arm. A 3D digital microscope coupled to the second support arm. A computer system including a processor programmed to receive and process images from the 3D digital microscope and display the processed images on the 3D digital viewport and the display monitor.

Abstract: A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that flexibly assigns memory access slots to access an external memory according to programmable information. A scheduler within an external memory interface assigns the memory access slots to the respective network switch ports according to a programmed sequence written into an assignment table memory from an external programmable data storage device.

Abstract: A number of network devices that control the communication of data frames between stations in a network are cascaded together to support a number of network stations. When a first device receives a data frame destined for a port on a second device, the first device transfers the data frame to the second device. The second device stores receive port information transmitted with the data frame and processes the data frame. If the second device identifies a congestion condition associated with processing the data, the second device transmits the receive port information back to the first device. The first device then performs a flow control-related operation on the port identified by the receive port information.

Abstract: A network switch configured for switching data packets across multiple ports uses numerous digital registers to process signals in support of the switch's functionalities. The design parameters associated with these registers are readily modifiable by storing these parameters in a central storage system. These design parameters are automatically read into the source code of a hardware description language, whereby the values and definitions of the registers are modified without altering the source code. Accordingly, any source code requiring updated bit definition and default values is automatically initialized without concern over design mismatch.

Abstract: An arrangement and method of operating a network switch arrangement in a packet switched network connects a plurality of multiport network switches which is in a circular, serial manner so that data is transferable between the network switches only unidirectionally. When it is determined that data is to be transmitted from a first network switch to a port in a second network switch, the data is transmitted over an expansion bus from the first network switch to the second network switch in a continuous stream of data bursts. This extremely fast transmission between the networks switches allows multiple multiport network switches to be cascaded together to effectively form a single network switch with at least twice as many ports.

Abstract: A network switch in a packet switched network includes a plurality of network switch ports, each configured for sending and receiving data packets between a medium interface and the network switch. The network switch port includes an IEEE 802.3 compliant transmit state machine and receive state machine configured for transmitting and receiving network data to and from a medium interface, such as a reduced medium independent interface, respectively. The network switch port also includes a memory management unit configured for selectively transferring the network data between the transmit and receive state machines and a random access transmit buffer and a random access receive buffer, respectively. The transmit state machine outputs a flush transmit buffer signal to the transmit memory management unit in response to a detected error in transmitting the transmit data.

Abstract: A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol dynamically allocates external memory bandwidth slots between high data rate ports. An external memory interface determines if a high data rate port makes a request for a bandwidth slot and grants the request if made. The slot is taken from a selected group which is a subset of the total number of slots. If a request for the slot is not made, the external memory interface assigns the slot to another high data rate port. Lower data rate ports in the network switch are assigned fixed slots from those slots not from within the selected group of slots. The dynamic allocation of bandwidth slots between the high data rate port enables the efficient use of limited memory bandwidth resources.

Abstract: A network switch having switch ports for full-duplex communication of data packets with respective network nodes according to Ethernet (IEEE 802.3) protocol that allocates a prescribed number of external memory bandwidth slots between high data rate ports based on the compared amount of network traffic on the respective ports. A scheduler within an external memory interface initially assigns memory access slots to the respective high data rate ports according to a prescribed sequence. If the scheduler subsequently detects that the network data traffic on a port having less slots is higher than the traffic on a port having more slots, the slots are swapped between the high data rate ports. Additionally, a clock multiplexer in one of the high data rate ports adjusts the data rate of the port dependent upon the number of slots assigned to that port.

Abstract: A method and apparatus are disclosed for testing the functionality of a queue structure. An input circuit is provided for inputting data into an input portion of the queue structure, while an output circuit is provided for retrieving data from an output portion of the queue structure. A comparison logic circuit compares the retrieved data with the input data to determine the integrity of the data that was stored in the queue structure and verify that the data from the output portion is identical to the data input to the queue. Various embodiments are disclosed for testing queue structure both in real time and in a test mode.

Abstract: A method and apparatus for programmably driving a light-emitting diode(LED) display stores a display configuration in a register. The register contains the information identifying for which conditions in the system will status information be provided to LED drivers. When used in a system such as an Ethernet network multiport switch, for example, the status information for only those conditions and those ports identified by the display configuration stored in the configuration register will be displayed, even though status is collected for more conditions in the system.

Abstract: An integrated multiport switch having an interface connected between the MAC of each port and a MIB report bus, whereby MIB reports for the plurality of switch ports are transmitted individually to a switch MIB engine, fed by the MIB report bus, on a time shared basis. The interface prioritizes transmission of the MIB reports to the MIB engine in accordance with the transmission characteristics associated with the respective ports. A FIFO storage buffer in interface temporarily holds MIB report data, received from lower priority ports on a time-slot allotted sequence synchronized to a clock signal, during periods in which MIB report data from higher priority ports are given preference for output to the MIB report bus.

Abstract: An integrated multiport switch (IMS) in which an on-chip management information base (MIB) accumulation processor enables monitoring of a significantly larger number of MIB objects to be stored in external memory while minimizing, media access controller (MAC) complexity. A MAC for each port in the IMS outputs a MIB report for each transmission or reception of data according to a specific compressed format to a MIB engine that can be centrally located on the chip. The compression of the data that represents the monitored events enables conservation of the capacity of MAC buffer elements. The MIB report is immediately dispatched to the MIB engine upon receipt or transmission of a data frame. The MIB engine decodes the MIB report into a plurality of associated MIB objects. which are temporarily accumulated until the external memory is updated.

Abstract: Every external physical layer device coupled to a multiport data communication switch is polled in succession to determine status and control information relating to the external physical layer device. The polling procedure performed automatically at regular time intervals is interleaved with management accesses to the external PHYs initiated by a host processor. The host management access may be performed to write or read management data to or from a particular register in a particular external physical layer device.