Abstract: In one embodiment, an impedance matching network includes a variable reactance circuit having fixed reactance components and corresponding switching circuits. Each switching circuit includes a diode and a driver circuit. The driver circuit includes, coupled in series, a biasing current source positioned to provide a bias current to bias the diode, a first switch, a second switch, and a resistor. For each diode of each switching circuit, the control circuit is configured to receive a value related to a voltage drop on the resistor and, based on the value related to the voltage drop, adjust the bias current being provided by the biasing current source.

Abstract: In one embodiment, an impedance matching network includes a variable reactance circuit providing a variable capacitance or inductance. The variable reactance circuit includes reactance components and corresponding switching circuits. Each of the switching circuits includes a diode and a driver circuit to switch the diode. The driver circuit includes first and second switches coupled in series. A first driver is coupled to the first switch, a second driver is coupled to the second switch, and a third driver is coupled to the first and second drivers. The third driver provides a first signal to the first driver, and a second signal to the second driver. In providing the signals, the third driver increases and decreases a duration of a dead time between (a) driving the first driver on and the second driver off, or (b) driving the second driver on and the first driver off.

Abstract: In one embodiment, an impedance matching network includes a variable reactance circuit providing a variable capacitance or inductance. The variable reactance circuit includes reactance components and corresponding switching circuits. Each of the switching circuits includes a diode and a driver circuit to switch the diode. The driver circuit includes first and second switches coupled in series. A first driver is coupled to the first switch, a second driver is coupled to the second switch, and a third driver is coupled to the first and second drivers. The third driver provides a first signal to the first driver, and a second signal to the second driver. In providing the signals, the third driver increases and decreases a duration of a dead time between (a) driving the first driver on and the second driver off, or (b) driving the second driver on and the first driver off.

Abstract: In one embodiment, an impedance matching network includes at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC. Each switch includes a first terminal operably coupled to the corresponding discrete capacitor, a second terminal, and a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising a switching transistor. A tuning inductor is coupled parallel to the switching circuit. A value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit.

Abstract: In one embodiment, a parasitic capacitance compensation circuit for a switch is disclosed that includes a first inductor operably coupled between a first terminal and a second terminal, and a second inductor operably coupled between the first and second terminals and parallel to the first inductor. The second inductor is switched in when a peak voltage on the first and second terminals falls below a first voltage. The first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage. The first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.

Abstract: In one embodiment, an impedance matching network is disclosed that includes a first circuit comprising a first variable component providing a first variable capacitance or inductance, and a second circuit comprising a second variable component providing a second variable capacitance or inductance. Each of the first circuit and the second circuit includes plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance. Each of the plurality of switching circuits includes a diode and a driver circuit configured to switch the diode. The driver circuit includes a first switch, a second switch coupled in series with the first switch, and a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode.

Abstract: In one embodiment, an impedance matching network includes at least one electronically variable capacitor (EVC), each EVC comprising discrete capacitors having corresponding switches, the switches configured to switch in and out the discrete capacitors to alter a total capacitance of the EVC. Each switch includes a first terminal operably coupled to the corresponding discrete capacitor, a second terminal, and a switching circuit coupled between the first terminal and the second terminal, the switching circuit comprising a switching transistor. A tuning inductor is coupled parallel to the switching circuit. A value for the tuning inductor enables the tuning inductor to cancel a cumulative parasitic capacitance of the switching circuit.

Abstract: In one embodiment, a parasitic capacitance compensation circuit for a switch is disclosed that includes a first inductor operably coupled between a first terminal and a second terminal, and a second inductor operably coupled between the first and second terminals and parallel to the first inductor. The second inductor is switched in when a peak voltage on the first and second terminals falls below a first voltage. The first inductance tunes out substantially all of a parasitic capacitance of the switch when the switch is OFF and the peak voltage is above the first voltage. The first and second inductances collectively tune out substantially all of the parasitic capacitance of the switch when the switch is OFF and the peak voltage is below the first voltage.

Abstract: In one embodiment, an impedance matching network is disclosed that includes a first circuit comprising a first variable component providing a first variable capacitance or inductance, and a second circuit comprising a second variable component providing a second variable capacitance or inductance. Each of the first circuit and the second circuit includes plurality of switching circuits configured to provide the first variable capacitance or inductance and the second variable capacitance or inductance. Each of the plurality of switching circuits includes a diode and a driver circuit configured to switch the diode. The driver circuit includes a first switch, a second switch coupled in series with the first switch, and a filter circuit that is coupled at a first end between the first switch and the second switch, and is operably coupled at a second end to the diode.