Patents by Inventor Ian M. Flanagan

Ian M. Flanagan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Delay-locked loop with built-in self-test of phase margin
    Patent number: 7042971
    Abstract: A method and apparatus for measuring phase margin of a delay-locked loop (DLL) is provided in which a reference clock is applied to a reference input of the DLL. An auxiliary variable delay is coupled within the DLL and is varied until the DLL becomes unstable. A phase margin output is generated as a function of a value of the variable delay at which the DLL becomes unstable.
    Type: Grant
    Filed: June 12, 2001
    Date of Patent: May 9, 2006
    Assignee: LSI Logic Corporation
    Inventors: Ian M. Flanagan, Roger L. Roisen, Dayanand K. Reddy, Joel J. Christiansen