Patents by Inventor Ian M. Williams
Ian M. Williams has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9053559Abstract: A method and system for presenting image data to a video output device is disclosed. One embodiment of the present invention sets forth a method, which includes the steps of queuing the buffer of image data for display, attaching an object to a command associated with presenting the buffer of image data, wherein the object is capable of storing timing information relating to executing the command, and enabling an application program to access the timing information.Type: GrantFiled: November 16, 2007Date of Patent: June 9, 2015Assignee: NVIDIA CorporationInventors: James Jones, Jeffrey F. Juliano, Robert Morell, Thomas True, Ian M. Williams
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Patent number: 8854380Abstract: One embodiment of the present invention sets forth a technique for displaying high-resolution images using multiple graphics processing units (GPUs). The graphics driver is configured to present one virtual display device, simulating a high-resolution mosaic display surface, to the operating system and the application programs. The graphics driver is also configured to partition the display surface amongst the GPUs and transmit commands and data to the local memory associated with the first GPU. A video bridge automatically broadcasts this information to the local memories associated with the remaining GPUs. Each GPU renders and displays only the partition of the display surface assigned to that particular GPU, and the GPUs are synchronized to ensure the continuity of the displayed images. This technique allows the system to display higher resolution images than the system hardware would otherwise support, transparently to the operating system and the application programs.Type: GrantFiled: September 13, 2013Date of Patent: October 7, 2014Assignee: NVIDIA CorporationInventors: Franck R. Diard, Ian M. Williams, Eric Boucher
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Publication number: 20140078148Abstract: One embodiment of the present invention sets forth a technique for displaying high-resolution images using multiple graphics processing units (GPUs). The graphics driver is configured to present one virtual display device, simulating a high-resolution mosaic display surface, to the operating system and the application programs. The graphics driver is also configured to partition the display surface amongst the GPUs and transmit commands and data to the local memory associated with the first GPU. A video bridge automatically broadcasts this information to the local memories associated with the remaining GPUs. Each GPU renders and displays only the partition of the display surface assigned to that particular GPU, and the GPUs are synchronized to ensure the continuity of the displayed images. This technique allows the system to display higher resolution images than the system hardware would otherwise support, transparently to the operating system and the application programs.Type: ApplicationFiled: September 13, 2013Publication date: March 20, 2014Applicant: NVIDIA CorporationInventors: Franck R. DIARD, Ian M. WILLIAMS, Eric BOUCHER
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Patent number: 8537166Abstract: One embodiment of the present invention sets forth a technique for displaying high-resolution images using multiple graphics processing units (GPUs). The graphics driver is configured to present one virtual display device, simulating a high-resolution mosaic display surface, to the operating system and the application programs. The graphics driver is also configured to partition the display surface amongst the GPUs and transmit commands and data to the local memory associated with the first GPU. A video bridge automatically broadcasts this information to the local memories associated with the remaining GPUs. Each GPU renders and displays only the partition of the display surface assigned to that particular GPU, and the GPUs are synchronized to ensure the continuity of the displayed images. This technique allows the system to display higher resolution images than the system hardware would otherwise support, transparently to the operating system and the application programs.Type: GrantFiled: December 6, 2007Date of Patent: September 17, 2013Assignee: NVIDIA CorporationInventors: Franck R. Diard, Ian M. Williams, Eric Boucher
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Patent number: 8212826Abstract: Disclosed are an apparatus, a computer device, a system, computer readable media and a method for using graphics processing unit (“GPU”)-generated data to characterize, in-situ, the ability of a cable to reliably carry digitized video, among other things. In one embodiment, a computing device includes a processor coupled via a system bus to a graphics engine and a video cable-testing apparatus. This apparatus has an input port configured to couple to the digitized video cable to receive pixel data generated by the graphics engine. It also has a signal integrity evaluator (“SIE”) configured to identify the digitized video cable as the source an amount of data corruption, the amount of data corruption being a function of the pixel data. The signal integrity evaluator includes a classifier to classify the amount of data corruption into classes that each represents various degrees of degradation of the computer-generated video images.Type: GrantFiled: February 3, 2006Date of Patent: July 3, 2012Assignee: NVIDIA CorporationInventors: Ian M. Williams, Dat T. Nguyen, Lauro B. Mañalac, Thomas J. True
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Patent number: 8031197Abstract: Disclosed are a GPU video data preprocessor, a computer device, an apparatus and a method for facilitating expeditious video transfer to graphics memory for enhancing display and video capture applications, among other things. In one embodiment, a graphics preprocessor is used to preprocess video for transit via a graphics processing unit (“GPU”) directly to graphics memory without invoking a graphics driver. The graphics preprocessor includes an input configured to receive video data. It also includes a native data formatter coupled to the input and configured to format the video data as GPU data to conform with the architecture of the GPU. In at least one embodiment, the graphics preprocessor also includes a command execution unit, which can be configured to transmit an instruction executable by the GPU as a transmitted instruction to perform a graphics pipeline operation on the GPU data.Type: GrantFiled: February 3, 2006Date of Patent: October 4, 2011Assignee: Nvidia CorporationInventors: Ian M. Williams, Dat T. Nguyen, Lauro B. Mañalac, Thomas J. True
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Patent number: 7995003Abstract: One embodiment of the present invention sets forth a technique for displaying high-resolution images using multiple graphics processing units (GPUs). The graphics driver is configured to present one virtual display device, simulating a high-resolution mosaic display surface, to the operating system and the application programs. The graphics driver is also configured to partition the display surface amongst the GPUs and transmit commands and data to the local memory associated with the first GPU. A video bridge automatically broadcasts this information to the local memories associated with the remaining GPUs. Each GPU renders and displays only the partition of the display surface assigned to that particular GPU, and the GPUs are synchronized to ensure the continuity of the displayed images. This technique allows the system to display higher resolution images than the system hardware would otherwise support, transparently to the operating system and the application programs.Type: GrantFiled: December 6, 2007Date of Patent: August 9, 2011Assignee: NVIDIA CorporationInventors: Franck R. Diard, Ian M. Williams, Eric Boucher
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Patent number: 7886337Abstract: Method and apparatus for protecting image content. In an embodiment, tags are used to identify how to alter image content. A graphics processor is configured to process the tags and to alter the image responsive to the tags. In another embodiment, a graphics processor is configured to alter image content unless a key is provided to the graphics processor.Type: GrantFiled: October 22, 2003Date of Patent: February 8, 2011Assignee: NVIDIA CorporationInventors: Ian M. Williams, Michael B. Diamond
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Patent number: 7859542Abstract: A method for synchronizing two of more graphics processing units. The method includes the steps of determining whether the phase of a first timing signal of a first graphics processing unit and the phase of a second timing signal of a second graphics processing unit are synchronized, and adjusting the frequency of the first timing signal to the frequency of the second timing signal if the first timing signal and the second timing signal are not synchronized.Type: GrantFiled: December 4, 2007Date of Patent: December 28, 2010Assignee: NVIDIA CorporationInventors: Ian M. Williams, Dat T. Nguyen, Jeffrey Chandler Doughty, Ralf Biermann, Kenneth Leon Adams, Jr., Andrew B. Ritger, Satish D. Salian, Fred D. Nicklisch
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Patent number: 7483031Abstract: A method for synchronizing two of more graphics processing units. The method includes the steps of determining whether the phase of a first timing signal of a first graphics processing unit and the phase of a second timing signal of a second graphics processing unit are synchronized, and adjusting the frequency of the first timing signal to the frequency of the second timing signal if the first timing signal and the second timing signal are not synchronized.Type: GrantFiled: December 8, 2003Date of Patent: January 27, 2009Assignee: NVIDIA CorporationInventors: Ian M. Williams, Dat T. Nguyen, Jeffrey Chandler Doughty, Ralf Biermann, Kenneth Leon Adams, Jr., Andrew B. Ritger, Satish D. Salian, Fred D. Nicklisch
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Patent number: 7205997Abstract: A method and system for converting an image data generated by a graphics subsystem into a video format. In one embodiment, the method includes generating the image data, storing the image data in a buffer, capturing the buffer to convert the image data to a texture, mapping the texture to at least one polygon to create a formatted image, and converting the formatted image to a stream of data in the video format.Type: GrantFiled: September 28, 2004Date of Patent: April 17, 2007Assignee: NVIDIA CorporationInventors: Ian M. Williams, Thomas True, Adrian Muntianu
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Patent number: 7159112Abstract: Encrypted graphics data is transmitted between systems or components of a system. The data is decrypted within a graphics processor or other recipient device that has been provided with an appropriate key. In one embodiment, encryption is performed by perturbing selected parameters of the graphics data so that the encrypted data can be used to generate a distorted image, and decryption is performed by reversing the perturbation.Type: GrantFiled: August 26, 2003Date of Patent: January 2, 2007Assignee: NVIDIA CorporationInventor: Ian M. Williams
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Patent number: 7120816Abstract: A method for testing synchronization between a first graphics processing unit coupled to a second graphics processing unit. The method includes detecting whether an incoming synchronization signal has been received, determining whether the incoming synchronization signal is received from one of the first graphics processing unit, the second graphics processing unit and an external synchronization signal, and indicating on a control panel one of a first and second synchronization input/output ports on one of the first graphics processing unit and the second graphics processing unit as an input port and the other one of the first and second synchronization input/output ports as an output port, if the incoming synchronization signal is received from the one of the first graphics processing unit and the second graphics processing unit.Type: GrantFiled: December 5, 2003Date of Patent: October 10, 2006Assignee: NVIDIA CorporationInventors: Ian M. Williams, Dat T. Nguyen, Jeffrey Chandler Doughty, Satish D. Salian
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Patent number: 7068278Abstract: A graphics processing unit, which includes a clock generator configured to generate a clock signal and a controller coupled to the clock generator. The controller is configured to receive the clock signal, compare the clock signal with a synchronization signal to generate a timing signal, and transmit the timing signal to a second graphics processing unit connected to the graphics processing unit.Type: GrantFiled: December 11, 2003Date of Patent: June 27, 2006Assignee: NVIDIA CorporationInventors: Ian M. Williams, Dale Ah Tye, Jeffrey J. Irwin, John S. Montrym, Michael Diamond
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Patent number: 6882347Abstract: The present invention provides an apparatus, system, and method for performing interference checking of the design in a project, component or part thereof to a designer, engineer, team of designers, or a team of engineers. In one embodiment, the present invention is comprised of a texture generating apparatus adapted to provide proximity analysis of objects in a design by dynamically generating a texture visually indicative of the spatial relationship between the modeled objects. In this embodiment, the texture generating apparatus is further comprised of a processing element. The processing element is adapted to perform the calculations of the interference check. The texture generating apparatus is further comprising a texture generating element. The texture generating element is adapted to provide the texture on which the interference check is based. The texture generating apparatus is further comprised a rendering element.Type: GrantFiled: November 30, 2000Date of Patent: April 19, 2005Assignee: Microsoft CorporationInventor: Ian M. Williams
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Publication number: 20040207618Abstract: A method for synchronizing two of more graphics processing units. The method includes the steps of determining whether the phase of a first timing signal of a first graphics processing unit and the phase of a second timing signal of a second graphics processing unit are synchronized, and adjusting the frequency of the first timing signal to the frequency of the second timing signal if the first timing signal and the second timing signal are not synchronized.Type: ApplicationFiled: December 8, 2003Publication date: October 21, 2004Applicant: NVIDIA CorporationInventors: Ian M. Williams, Dat T. Nguyen, Jeffrey Chandler Doughty, Ralf Biermann, Kenneth Leon Adams, Andrew B. Ritger, Satish D. Salian, Fred D. Nicklisch
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Publication number: 20040210788Abstract: A method for testing synchronization between a first graphics processing unit coupled to a second graphics processing unit. The method includes detecting whether an incoming synchronization signal has been received, determining whether the incoming synchronization signal is received from one of the first graphics processing unit, the second graphics processing unit and an external synchronization signal, and indicating on a control panel one of a first and second synchronization input/output ports on one of the first graphics processing unit and the second graphics processing unit as an input port and the other one of the first and second synchronization input/output ports as an output port, if the incoming synchronization signal is received from the one of the first graphics processing unit and the second graphics processing unit.Type: ApplicationFiled: December 5, 2003Publication date: October 21, 2004Applicant: NVIDIA CorporationInventors: Ian M. Williams, Dat T. Nguyen, Jeffrey Chandler Doughty, Satish D. Salian
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Patent number: 6545683Abstract: An apparatus and method is provided that increases the throughput of graphics commands transferred between a system bridge and a graphics subsystem. In one embodiment, the apparatus tags each of the multiple graphics commands to indicate a specific order of the multiple graphics commands. Each of the tagged multiple graphics commands are then assigned to one of a plurality of busses. The plurality of busses transfer each of the multiple graphics commands across its assigned one the plurality of busses. After being transferred across the plurality of busses, the multiple graphics commands are put back in their original specific order through the use of the tags. The reordered (also referred to as regrouped) multiple graphics commands are then transferred to the graphics subsystem. In another embodiment, multiple graphics commands are transferred over a plurality of busses to functional components of the graphics subsystem.Type: GrantFiled: April 19, 1999Date of Patent: April 8, 2003Assignee: Microsoft CorporationInventor: Ian M. Williams
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Publication number: 20020063720Abstract: The present invention provides an apparatus, system, and method for performing interference checking of the design in a project, component or part thereof to a designer, engineer, team of designers, or a team of engineers. In one embodiment, the present invention is comprised of a texture generating apparatus adapted to provide proximity analysis of objects in a design by dynamically generating a texture visually indicative of the spatial relationship between the modeled objects. In this embodiment, the texture generating apparatus is further comprised of a processing element. The processing element is adapted to perform the calculations of the interference check. The texture generating apparatus is further comprising a texture generating element. The texture generating element is adapted to provide the texture on which the interference check is based. The texture generating apparatus is further comprised a rendering element.Type: ApplicationFiled: November 30, 2000Publication date: May 30, 2002Inventor: Ian M. Williams
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Patent number: 6397343Abstract: In a computer system having a CPU and a graphics subsystem, a device for dynamic graphics subsystem clock adjustment. A clock pulse generator is used for generating a clock frequency. The clock frequency is coupled to the graphics subsystem and is used by the graphics subsystem to synchronize and pace its internal operations. The clock frequency generated by the generator is variable over a range. A controller is coupled to the clock pulse generator, for adjusting the clock frequency from the clock pulse generator over the range. The controller interfaces with the computer system through an interface coupled to the controller. Through the interface, the controller communicates with the computer system or graphics subsystem and determines a load placed on the graphics subsystem.Type: GrantFiled: March 19, 1999Date of Patent: May 28, 2002Assignee: Microsoft CorporationInventors: Ian M. Williams, Philip Cheng