Abstract: System and method for reducing access latency to a shared program memory. The program memory is shared by more than one processor. The system includes fetch buffers (one per processor), prefetch buffers (one per processor), program fetch logic units (one per processor), and an arbiter. Each fetch buffer stores local instructions that are local to an instruction being used by an associated processor. Each prefetch buffer stores subsequent instructions that are subsequent to the local instructions stored in an associated fetch buffer. Each program fetch logic unit determines from where to fetch a next instruction required by the associated processor. The arbiter arbitrates between instruction fetch requests received for the fetch buffers and the prefetch buffers from the various processors. The arbiter determines which of the instruction fetch requests will next gain access to the program memory.

Abstract: In a telecommunications system, an arithmetic logic unit (ALU) that receives an input signal. The input signal includes a digital signal representative of an analog signal. The ALU selectively performs compression and decompression on the digital signal. The ALU comprises the following elements. A standard ALU component performs standard ALU operations on the input signal. An encoding unit selectively performs compression on the digital signal. A decoding unit selectively performs decompression on the digital signal. An instruction decoder receives and decodes an ALU instruction. An output selector selects a result from one of the standard ALU component, the encoding unit, and the decoding unit in accordance with the decoded instruction and provides the result as an output.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline arhitecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: An asynchronously pipelined SDRAM has separate pipeline stages that are controlled by asynchronous signals. Rather than using a clock signal to synchronize data at each stage, an asynchronous signal is used to latch data at every stage. The asynchronous control signals are generated within the chip and are optimized to the different latency stages. Longer latency stages require larger delays elements, while shorter latency states require shorter delay elements. The data is synchronized to the clock at the end of the read data path before being read out of the chip. Because the data has been latched at each pipeline stage, it suffers from less skew than would be seen in a conventional wave pipeline architecture. Furthermore, since the stages are independent of the system clock, the read data path can be run at any CAS latency as long as the re-synchronizing output is built to support it.

Abstract: A power up, power down reset circuit formed of charge storage apparatus for receiving and storing charge from one pole of a voltage supply, a pair of complementary field effect transistors having source-drain circuits connected in series aiding direction between the charge storage apparatus and another pole of the voltage supply, apparatus for connecting the one pole of the voltage supply to a gate of one transistor of the pair of transistors, apparatus for applying a voltage derived from the one pole of the voltage supply but having a value reduced from voltage of the voltage supply, to a gate of another transistor of the pair of transistors, and apparatus for providing a reset pulse from a junction between the source-drain circuits of the pair of transistors.