Patents by Inventor Ian Milton

Ian Milton has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20180349544
    Abstract: An integrated circuit design may include registers and combinational logic. Integrated circuit design computing equipment may perform retiming for the circuit design, where registers are moved across one or more portions of the combinational logic. The registers may be retimed while considering hybrid initial states of the registers. At least some of the registers may have don't-care initial states. When performing backward retiming, initial states of the retimed registers may be computed that is consistent with the original initial state and functionality of the combinational logic while maximizing the number of don't-care initial states. When performing forward retiming across non-justifiable combinational elements, any don't-care initial states may be assumed to be equal to a deterministic binary value, and the initial states of the retimed registers may be computed that is consistent with the original initial states and functionality of the combinational logic.
    Type: Application
    Filed: May 31, 2017
    Publication date: December 6, 2018
    Applicant: Intel Corporation
    Inventors: Mahesh A. Iyer, Ian Milton, Dai Le
  • Patent number: 9811621
    Abstract: Circuit design computing equipment may perform depopulation operations, constraint generation, and repopulation operations in a circuit design in anticipation of register retiming operations. A depopulation operation before placement and/or before routing operations may prevent the respective placement and/or routing operations from placing and/or routing registers from the circuit design. Constraint generation may create constraints for placement and/or routing operations that allow for the reinsertion of registers after routing operations. Repopulation operations may reinsert registers in the circuit design after routing operations according to the constraints. If desired, the circuit design computing equipment may perform register retiming operations to further improve the performance of the circuit design.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: November 7, 2017
    Assignee: Altera Corporation
    Inventors: Kimberly Anne Bozman, David Ian Milton, Nishanth Sinnadurai
  • Publication number: 20160321390
    Abstract: Circuit design computing equipment may perform depopulation operations, constraint generation, and repopulation operations in a circuit design in anticipation of register retiming operations. A depopulation operation before placement and/or before routing operations may prevent the respective placement and/or routing operations from placing and/or routing registers from the circuit design. Constraint generation may create constraints for placement and/or routing operations that allow for the reinsertion of registers after routing operations. Repopulation operations may reinsert registers in the circuit design after routing operations according to the constraints. If desired, the circuit design computing equipment may perform register retiming operations to further improve the performance of the circuit design.
    Type: Application
    Filed: May 1, 2015
    Publication date: November 3, 2016
    Inventors: Kimberly Anne Bozman, David Ian Milton, Nishanth Sinnadurai
  • Patent number: 9098662
    Abstract: Techniques and mechanisms allow a device such as a programmable logic device (PLD) to support real-time debugging of a system. The PLD may be configured to include a debug design without disturbing the configuration of a base logic design in the PLD.
    Type: Grant
    Filed: August 28, 2013
    Date of Patent: August 4, 2015
    Assignee: Altera Corporation
    Inventors: Gordon Raymond Chiu, Jason Peters, David Ian Milton