Abstract: Techniques are disclosed relating to polynomial approximation of the base-2 logarithm. In some embodiments, floating-point circuitry is configured to perform an approximation of a base-2 logarithm operation and provide a fixed unit of least precision (ULP) error over a range of inputs. In some embodiments, the floating-point circuitry includes a set of parallel pipelines for polynomial approximation, where the output is chosen from a particular pipeline based on a determination of whether the input operand is in a first subset of a range of inputs. Disclosed techniques may advantageously provide fixed ULP error for an entire input operand range for the floating-point base-2 logarithmic function with minimal area and energy footprint, relative to traditional techniques.

Abstract: Techniques are disclosed relating to circuitry for floating-point division. In some embodiments, the circuitry is configured to generate a subnormal result for a division operation that divides a numerator by a denominator. The circuitry may include floating-point circuitry configured to perform a reciprocal operation to determine a normalized mantissa value for the reciprocal of a floating-point representation of the denominator. The circuitry may further include fixed-point circuitry configured to multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value. Control circuitry may determine error data for the initial value and generate a final subnormal mantissa result for the division operation based on the error data and the initial value. Embodiments with multiple modes with different accuracy guarantees are disclosed.

Abstract: Techniques are disclosed relating to circuitry for floating-point division. In some embodiments, the circuitry is configured to generate a subnormal result for a division operation that divides a numerator by a denominator. The circuitry may include floating-point circuitry configured to perform a reciprocal operation to determine a normalized mantissa value for the reciprocal of a floating-point representation of the denominator. The circuitry may further include fixed-point circuitry configured to multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value. Control circuitry may determine error data for the initial value and generate a final subnormal mantissa result for the division operation based on the error data and the initial value. Embodiments with multiple modes with different accuracy guarantees are disclosed.

Abstract: Techniques are disclosed relating to circuitry for floating-point division. In some embodiments, the circuitry is configured to generate a subnormal result for a division operation that divides a numerator by a denominator. The circuitry may include floating-point circuitry configured to perform a reciprocal operation to determine a normalized mantissa value for the reciprocal of a floating-point representation of the denominator. The circuitry may further include fixed-point circuitry configured to multiply a fixed-point representation of the normalized mantissa value for the reciprocal by a mantissa of the numerator to generate an initial value. Control circuitry may determine error data for the initial value and generate a final subnormal mantissa result for the division operation based on the error data and the initial value. Embodiments with multiple modes with different accuracy guarantees are disclosed.

Abstract: Techniques are disclosed relating to floating-point circuitry configured to perform a corner check instruction for a floating-point power operation. In some embodiments, the power operation is performed by executing multiple instructions, including one or more instructions specify to generate an initial power result of a first input raised to the power of a second input as 2(second input*log2(first input)). In some embodiments, the corner check instruction operates on the first and second inputs and outputs output a corrected power result based on detection of a corner condition for the first and second inputs. Corner check circuitry may share circuits with other datapaths. In various embodiments, the disclosed techniques may reduce code size and power consumption for the power operation.

Abstract: Techniques are disclosed relating to floating-point circuitry configured to perform a corner check instruction for a floating-point power operation. In some embodiments, the power operation is performed by executing multiple instructions, including one or more instructions specify to generate an initial power result of a first input raised to the power of a second input as 2(second input*log2(first input)). In some embodiments, the corner check instruction operates on the first and second inputs and outputs output a corrected power result based on detection of a corner condition for the first and second inputs. Corner check circuitry may share circuits with other datapaths. In various embodiments, the disclosed techniques may reduce code size and power consumption for the power operation.

Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.

Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.

Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.

Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.

Abstract: A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic processing unit may be instructed to perform a floating point add operation to generate a sum in the first floating point format from the addend and the first representation. A second representation of the number in a second floating point format may be extracted directly from the sum. The first floating point format and the second floating point format may be based on different precisions for the first and second representation of the number.

Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.

Abstract: A method and an apparatus that determine an addend in a first floating point format from a first representation of a number in the first floating point format are described. An arithmetic processing unit may be instructed to perform a floating point add operation to generate a sum in the first floating point format from the addend and the first representation. A second representation of the number in a second floating point format may be extracted directly from the sum. The first floating point format and the second floating point format may be based on different precisions for the first and second representation of the number.

Abstract: A method and an apparatus for a parallel computing program using subbuffers to perform a data processing task in parallel among heterogeneous compute units are described. The compute units can include a heterogeneous mix of central processing units (CPUs) and graphic processing units (GPUs). A system creates a subbuffer from a parent buffer for each of a plurality of heterogeneous compute units. If a subbuffer is not associated with the same compute unit as the parent buffer, the system copies data from the subbuffer to memory of that compute unit. The system further tracks updates to the data and transfers those updates back to the subbuffer.

Abstract: Methods and apparatus for providing a scroll bar including a plurality of locations corresponding to a plurality of locations in a file are disclosed. One or more location criteria that are obtained are used to identify one or more desired locations in the file. One or more display criteria to be applied to designate the one or more desired locations are identified. In addition, one or more desired locations in the file are located according to the location criteria. The scroll bar is then displayed by applying the display criteria to one or more locations of the scroll bar corresponding to the desired locations in the file.

Abstract: The present invention provides prodrugs of GABA analogs, pharmaceutical compositions of prodrugs of GABA analogs and methods for making prodrugs of GABA analogs. The present invention also provides methods for using prodrugs of GABA analogs and methods for using pharmaceutical compositions of prodrugs of GABA analogs for treating or preventing common diseases and/or disorders.

Abstract: The present invention provides prodrugs of GABA analogs, pharmaceutical compositions of prodrugs of GABA analogs and methods for making prodrugs of GABA analogs. The present invention also provides methods for using prodrugs of GABA analogs and methods for using pharmaceutical compositions of prodrugs of GABA analogs for treating or preventing common diseases and/or disorders.

Abstract: A method and system to rotate a 2N by 2N array are described. Consistent with one embodiment of the present invention, the 2N elements of the 2N rows of a 2N by 2N array are loaded from memory into the vector registers of a processor's single instruction multiple data (SIMD) unit. Next, the elements of the rows in the top half of the array are interleaved with corresponding elements from a corresponding row in the bottom half of the array. The loading and interleaving operations are repeated N times before the results, stored in the vector registers, are written back to memory.

Abstract: A method and system to rotate a 2N by 2N array are described. Consistent with one embodiment of the present invention, the 2N elements of the 2N rows of a 2N by 2N array are loaded from memory into the vector registers of a processor's single instruction multiple data (SIMD) unit. Next, the elements of the rows in the top half of the array are interleaved with corresponding elements from a corresponding row in the bottom half of the array. The loading and interleaving operations are repeated N times before the results, stored in the vector registers, are written back to memory.

Abstract: A method and system to rotate a 2N by 2N array are described. Consistent with one embodiment of the present invention, the 2N elements of the 2N rows of a 2N by 2N array are loaded from memory into the vector registers of a processor's single instruction multiple data (SIMD) unit. Next, the elements of the rows in the top half of the array are interleaved with corresponding elements from a corresponding row in the bottom half of the array. The loading and interleaving operations are repeated N times before the results, stored in the vector registers, are written back to memory.