Patents by Inventor Ian R. Post
Ian R. Post has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8741720Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: GrantFiled: April 5, 2013Date of Patent: June 3, 2014Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Publication number: 20130224926Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: ApplicationFiled: April 5, 2013Publication date: August 29, 2013Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chai-Hong Jan, Mark T. Bohr
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Patent number: 8426927Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: GrantFiled: May 13, 2011Date of Patent: April 23, 2013Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Patent number: 8174060Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: GrantFiled: March 4, 2011Date of Patent: May 8, 2012Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Patent number: 8154067Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: GrantFiled: April 6, 2009Date of Patent: April 10, 2012Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Publication number: 20110215422Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: ApplicationFiled: May 13, 2011Publication date: September 8, 2011Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Publication number: 20110157854Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: ApplicationFiled: March 4, 2011Publication date: June 30, 2011Inventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Patent number: 7943468Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: GrantFiled: March 31, 2008Date of Patent: May 17, 2011Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Publication number: 20090242998Abstract: A semiconductor device and method to form a semiconductor device is described. The semiconductor includes a gate stack disposed on a substrate. Tip regions are disposed in the substrate on either side of the gate stack. Halo regions are disposed in the substrate adjacent the tip regions. A threshold voltage implant region is disposed in the substrate directly below the gate stack. The concentration of dopant impurity atoms of a particular conductivity type is approximately the same in both the threshold voltage implant region as in the halo regions. The method includes a dopant impurity implant technique having sufficient strength to penetrate a gate stack.Type: ApplicationFiled: March 31, 2008Publication date: October 1, 2009Inventors: Giuseppe Curello, Ian R. Post, Nick Lindert, Walid M. Hafez, Chia-Hong Jan, Mark T. Bohr
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Publication number: 20090189193Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: ApplicationFiled: April 6, 2009Publication date: July 30, 2009Applicant: INTEL CORPORATIONInventors: GIUSEPPE CURELLO, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Patent number: 7560780Abstract: A semiconductor device and method for its fabrication are described. An active region spacer may be formed on a top surface of an isolation region and adjacent to a sidewall of an active region. In one embodiment, the active region spacer may suppress the formation of metal pipes in the active region.Type: GrantFiled: December 8, 2005Date of Patent: July 14, 2009Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Sunit Tyagi, Mark Bohr
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Patent number: 7541239Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: GrantFiled: June 30, 2006Date of Patent: June 2, 2009Assignee: Intel CorporationInventors: Giuseppe Curello, Ian R. Post, Chia-Hong Jan, Mark Bohr
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Publication number: 20080003746Abstract: A method of selectively forming a spacer on a first class of transistors and devices formed by such methods. The method can include depositing a conformal first deposition layer on a substrate with different classes of transistors situated thereon, depositing a blocking layer to at least one class of transistors, dry etching the first deposition layer, removing the blocking layer, depositing a conformal second deposition layer on the substrate, dry etching the second deposition layer and wet etching the remaining first deposition layer. Devices may include transistors of a first class with larger spacers compared to spacers of transistors of a second class.Type: ApplicationFiled: June 30, 2006Publication date: January 3, 2008Inventors: Giuseppe Curello, Ian R. Post, Chai-Hong Jan, Mark Bohr
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Patent number: 7226843Abstract: A method including forming a transistor device having a channel region; implanting a first halo into the channel region; and implanting a second different halo into the channel region. An apparatus including a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant including a different second species in the channel region.Type: GrantFiled: September 30, 2002Date of Patent: June 5, 2007Assignee: Intel CorporationInventors: Cory E. Weber, Gerhard Schrom, Ian R. Post, Mark A. Stettler
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Patent number: 6979609Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.Type: GrantFiled: April 30, 2003Date of Patent: December 27, 2005Assignee: Intel CorporationInventors: Ian R. Post, Kaizad Mistry
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Patent number: 6803285Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.Type: GrantFiled: December 4, 2002Date of Patent: October 12, 2004Assignee: Intel CorporationInventors: Kaizad R. Mistry, Ian R. Post
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Patent number: 6717221Abstract: An apparatus including a MOSFET circuit having dual threshold voltage NMOS and PMOS transistors wherein the threshold voltage of a low threshold NMOS transistor is set with a first halo implant, a threshold voltage of a high threshold voltage PMOS transistor is set with a second halo implant, and, a threshold voltage of a high threshold voltage NMOS transistor is enhanced while, a threshold voltage of a low threshold voltage PMOS transistor is compensated with a third halo implant.Type: GrantFiled: April 30, 2003Date of Patent: April 6, 2004Assignee: Intel CorporationInventors: Ian R. Post, Kaizad Mistry
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Publication number: 20040061187Abstract: A method including forming a transistor device having a channel region; implanting a first halo into the channel region; and implanting a second different halo into the channel region. An apparatus including a gate electrode formed on a substrate; a channel region formed in the substrate below the gate electrode and between contact points; a first halo implant comprising a first species in the channel region; and a second halo implant including a different second species in the channel region.Type: ApplicationFiled: September 30, 2002Publication date: April 1, 2004Inventors: Cory E. Weber, Gerhard Schrom, Ian R. Post, Mark A. Stettler
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Patent number: 6693331Abstract: A method of forming an MOS integrated circuit having at least two types of NFET, each type having a different threshold voltage, and at least two types of PFET, each type having a different threshold voltage, includes forming at least four active regions in a substrate, each region having a different doping profile. A conventional two threshold voltage CMOS process is modified to produce four transistor threshold voltages with only one additional masked implant operation. This additional implant raises the threshold voltage of one type of MOSFET while lowering that of the other MOSFET type.Type: GrantFiled: November 18, 1999Date of Patent: February 17, 2004Assignee: Intel CorporationInventors: Kaizad R. Mistry, Ian R. Post
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Publication number: 20030203579Abstract: A method for processing dual threshold nMOSFETs and pMOSFETs requiring only one additional masking and implantation operation over single threshold MOSFETs is disclosed. The additional mask and implant operation both enhances the threshold voltage doping of one type of FET and compensates the threshold voltage doping of another type of FET. Where a first threshold voltage implant sets the threshold voltage for an NMOS device to a low threshold voltage, and a second threshold voltage implant sets the threshold voltage for a PMOS device to a high threshold voltage, a third implant may both enhance a NMOS device threshold implant to set the threshold voltage high while compensating a PMOS device threshold implant to set the threshold voltage low.Type: ApplicationFiled: April 30, 2003Publication date: October 30, 2003Inventors: Ian R. Post, Kaizad Mistry