Patents by Inventor Ian Robert Harvey

Ian Robert Harvey has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6249039
    Abstract: An inductive component includes a substrate on the surface of which is a lower insulation layer having a shallow concavity or trench, a first plurality of conductive elements formed in the trench, a magnetic core formed over the first plurality of conductive elements, and a second plurality of conductive elements formed over the core. The first and second pluralities of conductive elements are connected to each other so as to form an inductive coil around the core. First and second core insulation layers are disposed between the core and the first and second pluralities of conductive elements, respectively. The component is fabricated by a method in which it is built up in the trench using thin film techniques. A first array of conductors is patterned over the lower insulation layer, and a first core insulation layer is applied over the first conductor array. A magnetic core is formed on top of the first core insulation layer, and a second core insulation layer is applied over the core.
    Type: Grant
    Filed: September 10, 1998
    Date of Patent: June 19, 2001
    Assignee: Bourns, Inc.
    Inventors: Ian Robert Harvey, Michael Frederick Ehman, Malcolm Randall Harvey, James Craig Stephenson
  • Patent number: 6241587
    Abstract: A system for dislodging by-product agglomerations from a polishing pad of a chemical mechanical polishing (CMP) machine. The present invention is used in conjunction with a CMP machine that polishes semiconductor wafers. Specifically, an embodiment of the dislodging system in accordance with the present invention includes a megasonic nozzle which is adapted to effectively dislodge polishing by-product agglomerations and particles from the grooves and micro-pits of the surface of a polishing pad through the application of an output stream of extremely agitated fluid (e.g., deionized water). One embodiment of the megasonic nozzle in accordance with the present invention includes two piezoelectric transducers which operate at a resonant frequency to produce the extremely agitated stream of fluid. A fluid line is connected to the megasonic nozzle and a fluid source in order to convey fluid to the megasonic nozzle.
    Type: Grant
    Filed: February 13, 1998
    Date of Patent: June 5, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Charles Franklin Drill, Ian Robert Harvey
  • Patent number: 6215129
    Abstract: A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.
    Type: Grant
    Filed: December 1, 1997
    Date of Patent: April 10, 2001
    Assignee: VSLI Technology, Inc.
    Inventors: Ian Robert Harvey, Satyendra Sethi
  • Patent number: 6207543
    Abstract: A process for making an integrated circuit is disclosed. This technique includes electrically interconnecting a pair of adjacent transistors positioned along a semiconductor substrate by coating with an oxide layer, planarizing the layer, then forming a trench exposing a contact region for each transistor. This trench is filled with a metal, such as tungsten to provide an electrical interconnection of the contact regions. The metal is then planarized to be approximately coplanar with the planarized oxide layer. Metal gate electrodes are formed at the same time as the interconnection. Additional processing includes depositing an IMO layer over the planarized metal and oxide and defining additional interconnections through the IMO layer.
    Type: Grant
    Filed: June 30, 1997
    Date of Patent: March 27, 2001
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Xi-Wei Lin
  • Patent number: 6162650
    Abstract: A test device and method for determining parameters of a plurality of vias formed into a dielectric material making contact to a buried conductive layer. The present invention is comprised of a sample structure disposed within the material through which a plurality of vias are to be formed. The sample structure is adapted to enhance secondary electron yield from the via bottom during a scanning electron microscope examination of the vias. Additionally, the plurality of vias to be formed are disposed intentionally offset with respect to the sample structure. As a result, the enhanced secondary electron yield from the sample structure characterizes the degree of misalignment present in the via formation process. In so doing, the present invention simultaneously quantifies the critical dimension of the vias, the alignment/registration of the via formation process, and determines whether or not the vias are etched to a minimum desired depth.
    Type: Grant
    Filed: October 5, 1998
    Date of Patent: December 19, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Satyendra Sethi
  • Patent number: 6084305
    Abstract: A semiconductor device structure and method for producing a shaped etch-front during an etching process. In one embodiment, the present invention is comprised of a first layer of material which is disposed above a contact layer. In this embodiment, the first layer of material has a first etch rate. Next, the present invention deposits a second layer of material above at least a portion of the first layer of material. The second layer of material has a second etch rate which is faster than the first etch rate. Additionally, in the present invention, the first layer of material and the second layer of material have a sloped interfacial topography. The sloped interfacial topography of the present invention creates shaped etch-front during the etching of an opening extending through the first layer of material and the second layer of material.
    Type: Grant
    Filed: October 6, 1997
    Date of Patent: July 4, 2000
    Assignee: VLSI Technology, Inc.
    Inventor: Ian Robert Harvey
  • Patent number: 6080677
    Abstract: An isolation structure on an integrated circuit is formed using a shallow trench isolation process. A layer of buffer oxide is formed on a substrate. A layer of nitride is formed on the layer of buffer oxide. The layer of nitride and the layer of buffer oxide are patterned to form a trench area. The substrate including the trench area is subjected to a plasma comprising H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas to clean impurities on the trench area. The substrate is etched to form a trench within the trench area.
    Type: Grant
    Filed: December 30, 1997
    Date of Patent: June 27, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Calvin Gabriel, Ian Robert Harvey, Linda Leard
  • Patent number: 6060376
    Abstract: A gate region of a transistor is prepared for receiving a deposit of metal. A chemical mechanical polishing process is performed to reduce thickness of an insulation layer above the gate region. At the end of the chemical mechanical polishing process, a portion of the insulating layer remains above the gate region. An etch process is performed to remove the portion of the insulating layer remaining above the gate region. The etch process also removes a portion of polysilicon within the gate region and removes a top portion of spacers on either side of the gate region. A polysilicon selective etch-back is performed to remove an additional portion of the polysilicon within the gate region.
    Type: Grant
    Filed: January 12, 1998
    Date of Patent: May 9, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Calvin Gabriel, Xi-Wei Lin, Tammy Zheng, Linda Leard, Ian Robert Harvey
  • Patent number: 6027950
    Abstract: A method for preventing oxygen microloading of an SOG layer. In one embodiment of the present invention, hydrogen is introduced into an etching environment. An etching step is then performed within the etching environment. During the etching step an SOG layer overlying a TEOS layer is etched until at least a portion of the underlying TEOS layer is exposed. The etching step continues and etches at least some of the exposed portion of the TEOS layer. During etching, the etched TEOS layer releases oxygen. The hydrogen present in the etching environment scavenges the released oxygen. As a result, the released oxygen does not microload the SOG layer. Thus, the etchback rate of the SOG layer is not significantly affected by the released oxygen, thereby allowing for controlled etchback of the SOG layer.
    Type: Grant
    Filed: August 5, 1997
    Date of Patent: February 22, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Calvin Todd Gabriel
  • Patent number: 6013558
    Abstract: A method of isolating a semiconductor device by shallow trench isolation is provided by: (a) etching a trench into the surface of an integrated circuit; (b) depositing an oxide in the trench so that at least the upper portion of the oxide is silicon-rich; (c) providing a polysilicon gate electrode on the surface of the integrated circuit, with the gate electrode being provided substantially adjacent to the trench with a space between the trench and the gate electrode; (d) providing a spacer oxide to cover the trench oxide, the gate electrode and the space between the trench and the gate electrode, so that the spacer oxide has near-stoichiometric levels of silicon; and (e) etching the spacer oxide from the surface of the integrated circuit under conditions effective to selectively etch the spacer oxide from the upper surface of the integrated circuit and from the upper surface of the gate electrode without etching the trench oxide from the upper portion of the trench.
    Type: Grant
    Filed: August 6, 1997
    Date of Patent: January 11, 2000
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Calvin Todd Gabriel, Milind Ganesh Weling
  • Patent number: 5976987
    Abstract: A self-aligned contact etch and method for forming a self-aligned contact etch. In one embodiment, the present invention performs an oxide selective etch to form an opening originating at a top surface of a photoresist layer. The opening extends through an underlying oxide layer, and terminates at a top surface of a nitride layer which underlies the oxide layer. Next, the present invention performs a nitride selective etch to extend the opening through the nitride layer to an underlying contact layer. In the present invention, the nitride selective etch causes the photoresist layer to be etched/receded. The nitride selective etch of the present invention further causes the oxide layer to be etched at and near the opening at the interface between the photoresist layer and the oxide layer. As a result, the opening is rounded at the top edge thereof when the layer of photoresist is removed.
    Type: Grant
    Filed: October 3, 1997
    Date of Patent: November 2, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Calvin Todd Gabriel, Subhas Bothra
  • Patent number: 5895245
    Abstract: A method for preparing a semiconductor substrate and a polysilicon gate for subsequent silicide formation. In one embodiment, the present invention performs an oxide etch to remove oxide from source and drain diffusion regions of the semiconductor substrate and from the top surface of the polysilicon gate. Next, the present invention subjects the semiconductor substrate and the polysilicon gate to an ashing environment. In the present invention, the ashing environment is comprised of H.sub.2 O vapor, and a gaseous fluorocarbon or a fluorinated hydrocarbon gas. In so doing, contaminants introduced into the source and drain diffusion regions of the semiconductor substrate and into the top surface of the polysilicon gate during the oxide etch are removed. Next, the present invention performs a semiconductor wafer surface clean step. The semiconductor wafer surface clean step provides a semiconductor wafer surface which is substantially similar to a virgin silicon surface.
    Type: Grant
    Filed: June 17, 1997
    Date of Patent: April 20, 1999
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Xi-Wei Lin, Ramiro Solis
  • Patent number: 5821163
    Abstract: A method for preventing oxygen microloading of an SOG layer. In one embodiment of the present invention, hydrogen is introduced into an etching environment. An etching step is then performed within the etching environment. During the etching step an SOG layer overlying a TEOS layer is etched until at least a portion of the underlying TEOS layer is exposed. The etching step continues and etches at least some of the exposed portion of the TEOS layer. During etching, the etched TEOS layer releases oxygen. The hydrogen present in the etching environment scavenges the released oxygen. As a result, the released oxygen does not microload the SOG layer. Thus, the etchback rate of the SOG layer is not significantly affected by the released oxygen, thereby allowing for controlled etchback of the SOG layer.
    Type: Grant
    Filed: February 13, 1996
    Date of Patent: October 13, 1998
    Assignee: VLSI Technology, Inc.
    Inventors: Ian Robert Harvey, Calvin Todd Gabriel