Abstract: Methods for forming a patterned layer of amorphous carbon on a substrate are described. A layer of amorphous carbon may be formed on the substrate. A layer of electron sensitive resist may be formed on top of the amorphous carbon layer. A pattern transferred into the electron sensitive resist layer with an electron beam writing process is developed. During the electron beam writing process, electrons may be conducted away from the writing area through the amorphous carbon layer. The amorphous carbon layer may be etched through in at least one region defined by the pattern developed into the layer of electron sensitive resist material. For some embodiments, the amorphous carbon layer may be formed by chemical vapor deposition. For some embodiments, the layer of electron sensitive resist may be hydrogen silsesquioxane (HSQ).

Abstract: Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately 1. The air gap may generally be formed by depositing a dielectric material between the respective conductive elements, depositing a porous layer over the conductive elements and the dielectric material, and then stripping the dielectric material out of the space between the respective conductive elements through the porous layer, which leaves an air gap between the respective conductive elements. The dielectric material may be, for example, an amorphous carbon layer, the porous layer may be, for example, a porous oxide layer, and the stripping process may utilize a downstream hydrogen-based strip process, for example.

Abstract: Methods for forming a patterned layer of amorphous carbon on a substrate are described. A layer of amorphous carbon may be formed on the substrate. A layer of electron sensitive resist may be formed on top of the amorphous carbon layer. A pattern transferred into the electron sensitive resist layer with an electron beam writing process is developed. During the electron beam writing process, electrons may be conducted away from the writing area through the amorphous carbon layer. The amorphous carbon layer may be etched through in at least one region defined by the pattern developed into the layer of electron sensitive resist material. For some embodiments, the amorphous carbon layer may be formed by chemical vapor deposition. For some embodiments, the layer of electron sensitive resist may be hydrogen silsesquioxane (HSQ).

Abstract: Embodiments of the invention generally provide a method of forming an air gap between conductive elements of a semiconductor device, wherein the air gap has a dielectric constant of approximately 1. The air gap may generally be formed by depositing a dielectric material between the respective conductive elements, depositing a porous layer over the conductive elements and the dielectric material, and then stripping the dielectric material out of the space between the respective conductive elements through the porous layer, which leaves an air gap between the respective conductive elements. The dielectric material may be, for example, an amorphous carbon layer, the porous layer may be, for example, a porous oxide layer, and the stripping process may utilize a downstream hydrogen-based strip process, for example.

Abstract: A process for passivating, and optionally stripping and inhibiting corrosion of an etched substrate (20), is described. In the process, a substrate (20) having etchant byproducts (24) thereon, is placed into a vacuum chamber (52), and passivated in a multicycle passivation process comprising at least two passivating steps. In each passivating step, passivating gas is introduced into the vacuum chamber (52) and a plasma is generated from the passivating gas. When the substrate also has remnant resist (26) thereon, the resist (26) is stripped in a multicycle passivation and stripping process, each cycle including a passivating step and a stripping step. The stripping step is performed by introducing a stripping gas into the vacuum chamber (52) and generating a plasma from the stripping gas. In the multicycle process, the passivating and optional stripping steps, are repeated at least once in the same order that the steps were done.

Abstract: The invention comprises an improvement in the process wherein a polysilicon layer, which is formed over a step on an integrated circuit structure and masked with a photoresist, is anisotropically etched to remove the exposed portions of the polysilicon layer leaving sidewall residues of a polymerized silicon/oxide-containing material adjacent the polysilicon lines. The improvement comprises treating the integrated circuit substrate with an aqueous ammonium-containing base/peroxide solution to remove the residues of polymerized silicon/oxide-containing material, without undercutting the remaining polysilicon.

Abstract: A process is described for removing, from an integrated circuit structure, photoresist remaining after one or more metal etch steps which also removes or inactivates a sufficient amount of remaining chlorine-containing residues from the previous metal etch steps to inhibit corrosion of remaining metal for at least 24 hours. The process includes a first stripping step which comprises flowing NH.sub.3 gas through a microwave plasma generator into a stripping chamber which contains the integrated circuit structure while maintaining a plasma in the plasma generator. O.sub.2 gas (and optionally NH.sub.3 gas) is flowed through the plasma generator into the stripping chamber during a second step while maintaining the plasma in the plasma generator.

Abstract: A low pressure process is described for the anisotropic etching of a titanium or tantalum silicide layer formed over a polysilicon layer on a gate oxide layer, and then masked. The etch process is carried out at a low pressure of about 10 milliTorr to about 30 milliTorr using Cl.sub.2 and HBr etching gases, preferably only Cl.sub.2 at the etching gas, to etch the silicide without undercutting the mask layer. In a preferred embodiment, etch residues are also eliminated by the use of only Cl.sub.2 as the etching gas in the low pressure etch step. In the most prefferred embodiment, any bulges which might otherwise remain in the sidewalls of the underlying polysilicon layer, are also eliminated by using only HBr as the etching gas in the over-etch step, which is highly selective to oxide to protect the underlying gate oxide layer; resulting in an anisotropic etch of both the titanium/tantalum silicide and polysilicon layers, without leaving etch residues on the wafer surface.

Abstract: The invention comprises an improvement in the process wherein a polysilicon layer, which is formed over a step on an integrated circuit structure and masked with a photoresist, is anisotropically etched to remove the exposed portions of the polysilicon layer leaving sidewall residues of a polymerized silicon/oxide-containing material adjacent the polysilicon lines. The improvement comprises treating the integrated circuit substrate with an aqueous hydroxide/peroxide solution to remove the residues of polymerized silicon/oxide-containing material, without undercutting the remaining polysilicon.

Abstract: The invention comprises an improvement in the process wherein a polysilicon layer, which is formed over a step on an integrated circuit structure and masked with a photoresist, is anisotropically etched to remove the exposed portions of the polysilicon layer leaving residues of polysilicon adjacent to the step and residues of a polymerized silicon/oxide-containing material adjacent the sidewalls of the masked portions of the polysilicon layer. The improvement comprises treating the integrated circuit substrate with a dilute hydroxide solution to remove both the polysilicon residues and the residues of polymerized silicon/oxide-containing material.