Patents by Inventor Ian Shaeffer

Ian Shaeffer has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9170894
    Abstract: Systems and methods are provided for detecting and correcting address errors in a memory system. In the memory system, a memory device generates an error-detection code based on an address transmitted via an address bus and transmits the error-detection code to a memory controller. The memory controller transmits an error indication to the memory device in response to the error-detection code. The error indication causes the memory device to remove the received address and prevent a memory operation.
    Type: Grant
    Filed: March 7, 2014
    Date of Patent: October 27, 2015
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Craig E. Hampel
  • Patent number: 9165638
    Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.
    Type: Grant
    Filed: May 1, 2015
    Date of Patent: October 20, 2015
    Assignee: Rambus Inc.
    Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
  • Patent number: 9141472
    Abstract: A memory system that supports error detection and correction (EDC) coverage. The memory system includes a memory module with at least two groups of memory devices that store data and another memory device that stores error checking information (e.g., Error Correcting Code) for both groups of memory devices. The memory module also includes a memory buffer that determines an address for accessing the error checking information based on whether data is transferred with the first group of memory devices or the second group of memory devices. Alternatively, the memory controller may determine the address for accessing the error checking information to reduce or eliminate the need for a memory buffer.
    Type: Grant
    Filed: September 11, 2012
    Date of Patent: September 22, 2015
    Assignee: Rambus Inc.
    Inventors: Thomas J. Giovannini, Ian Shaeffer
  • Patent number: 9142281
    Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.
    Type: Grant
    Filed: April 28, 2015
    Date of Patent: September 22, 2015
    Assignee: Rambus Inc.
    Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
  • Publication number: 20150255144
    Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.
    Type: Application
    Filed: April 28, 2015
    Publication date: September 10, 2015
    Applicant: Rambus Inc.
    Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
  • Publication number: 20150248926
    Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.
    Type: Application
    Filed: May 18, 2015
    Publication date: September 3, 2015
    Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
  • Publication number: 20150243343
    Abstract: A system that calibrates timing relationships between signals involved in performing write operations is described. This system includes a memory controller which is coupled to a set of memory chips, wherein each memory chip includes a phase detector configured to calibrate a phase relationship between a data-strobe signal and a clock signal received at the memory chip from the memory controller during a write operation. Furthermore, the memory controller is configured to perform one or more write-read-validate operations to calibrate a clock-cycle relationship between the data-strobe signal and the clock signal, wherein the write-read-validate operations involve varying a delay on the data-strobe signal relative to the clock signal by a multiple of a clock period.
    Type: Application
    Filed: May 1, 2015
    Publication date: August 27, 2015
    Applicant: Rambus Inc.
    Inventors: Thomas J. Giovannini, Alok Gupta, Ian Shaeffer, Steven C. Woo
  • Publication number: 20150244370
    Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
    Type: Application
    Filed: February 11, 2015
    Publication date: August 27, 2015
    Inventor: Ian Shaeffer
  • Patent number: 9117496
    Abstract: A memory device comprising a programmable command-and-address (CA) interface and/or a programmable data interface is described. In an operational mode, two or more CA interfaces may be active. In another operational mode, at least one, but not all, CA interfaces may be active. In an operational mode, all of the data interfaces may be active. In another operational mode, at least one, but not all, data interfaces may be active. The memory device can include circuitry to select: an operational mode; a sub-mode within an operational mode; one or more CA interfaces as the active CA interface(s); a main CA interface from multiple active CA interfaces; and/or one or more data interfaces as the active data interfaces. The circuitry may perform these selection(s) based on one or more bits in one or more registers and/or one or more signals received on one or more pins.
    Type: Grant
    Filed: January 29, 2013
    Date of Patent: August 25, 2015
    Assignee: RAMBUS INC.
    Inventors: Ian Shaeffer, Lawrence Lai, Fan Ho, David A. Secker, Wayne S. Richardson, Akash Bansal, Brian S. Leibowitz, Kyung Suk Oh
  • Patent number: 9117035
    Abstract: Systems, among other embodiments, include topologies (data and/or control/address information) between an integrated circuit buffer device (that may be coupled to a master, such as a memory controller) and a plurality of integrated circuit memory devices. For example, data may be provided between the plurality of integrated circuit memory devices and the integrated circuit buffer device using separate segmented (or point-to-point link) signal paths in response to control/address information provided from the integrated circuit buffer device to the plurality of integrated circuit buffer devices using a single fly-by (or bus) signal path. An integrated circuit buffer device enables configurable effective memory organization of the plurality of integrated circuit memory devices. The memory organization represented by the integrated circuit buffer device to a memory controller may be different than the actual memory organization behind or coupled to the integrated circuit buffer device.
    Type: Grant
    Filed: August 30, 2013
    Date of Patent: August 25, 2015
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Ely Tsern, Craig Hampel
  • Patent number: 9098281
    Abstract: An integrated circuit includes a physical layer interface having a control timing domain and a data timing domain, and circuits that enable the control timing domain during a change in power conservation mode in response to a first event, and that enable the data timing domain in response to a second event. The control timing domain can include interface circuits coupled to a command and address path, and the data timing domain can include interface circuits coupled to a data path.
    Type: Grant
    Filed: March 8, 2012
    Date of Patent: August 4, 2015
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Lei Luo, Liji Gopalakrishnan
  • Publication number: 20150206562
    Abstract: A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.
    Type: Application
    Filed: March 30, 2015
    Publication date: July 23, 2015
    Inventor: Ian Shaeffer
  • Publication number: 20150170724
    Abstract: A system has a plurality of memory devices arranged in a fly-by topology, each having on-die termination (ODT) circuitry for connecting to an address and control (RQ) bus. The ODT circuitry of each memory device includes a set of one or more control registers for controlling on-die termination of one or more signal lines of the RQ bus. A first memory device includes a first set of one or more control registers storing a first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the first memory device, and a second memory device includes a second set of one or more control registers storing a second ODT value different from the first ODT value, for controlling termination of one or more signal lines of the RQ bus by the ODT circuitry of the second memory device.
    Type: Application
    Filed: February 3, 2015
    Publication date: June 18, 2015
    Inventors: Ian Shaeffer, Kyung Suk Oh
  • Publication number: 20150162101
    Abstract: A memory device (100) includes an extra column (114) of repair memory tiles. These repair memory tiles are accessed at the same time, and in the same manner as the main array of memory tiles. The output of the repair column is substituted for the output of a column of the main array (112). The main array column that is substituted is determined by tags (121) stored externally to the memory device. The external tags are queried with a partial address of the access. If the address of the access corresponds to an address in the external tags, the tag information is supplied to the memory device. The tag information determines which column in the main array is replaced by the output of the repair column. Since each column of the main array supplies one bit during the access, the repair column enables cell-by-cell replacement of main array cells.
    Type: Application
    Filed: October 31, 2013
    Publication date: June 11, 2015
    Inventors: Frederick A. Ware, Suresh Rajan, Ian Shaeffer
  • Publication number: 20150162092
    Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.
    Type: Application
    Filed: February 18, 2015
    Publication date: June 11, 2015
    Inventors: Brent Haukness, Ian Shaeffer
  • Patent number: 9025409
    Abstract: A memory module comprises a module interface having module data-group ports to communicate data as respective data groups, a command port to receive memory-access commands, a first memory device including a first device data-group port, a second memory device including a second device data-group port, and a signal buffer coupled between the module interface and each of the first and second devices. In a first mode, in response to the memory-access commands, the signal buffer communicates the data group associated with each of the first and second device data-group ports via a respective one of the module data-group ports. In a second mode, in response to the memory-access commands, the signal buffer alternatively communicates the data group associated with the first device data-group port or the data group associated with the second device data-group port via the same one of the module data-group ports.
    Type: Grant
    Filed: August 3, 2012
    Date of Patent: May 5, 2015
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 8988102
    Abstract: Local on-die termination controllers for effecting termination of a high-speed signaling links simultaneously engage on-die termination structures within multiple integrated-circuit memory devices disposed on the same memory module, and/or within the same integrated-circuit package, and coupled to the high-speed signaling link. A termination control bus is coupled to memory devices on a module, and provides for peer-to-peer communication of termination control signals.
    Type: Grant
    Filed: January 20, 2012
    Date of Patent: March 24, 2015
    Assignee: Rambus Inc.
    Inventor: Ian Shaeffer
  • Patent number: 8990485
    Abstract: This disclosure provides a method of accurately determining expected transaction times associated with flash memory subdivisions, such as devices, blocks or pages. By performing a test transaction to program each bit of each such unit, the maximum expected programming time of each unit may be determined in advance and used for scheduling purposes. For example, in a straightforward implementation, a relatively accurate, empirically measured time limit may be identified and used to efficiently manage and schedule flash memory transactions without awaiting ultimate resolution of attempts to write to a non-responsive page. This disclosure also provides other uses of empirically-measured maximum flash memory transaction times, including via multiple memory modes and prioritized memory; for example, if a high performance mode is desired, low variation in flash memory transaction times may be tolerated, and units not satisfying these principles may be marked relatively quickly.
    Type: Grant
    Filed: June 13, 2013
    Date of Patent: March 24, 2015
    Assignee: Rambus Inc.
    Inventors: Brent Haukness, Ian Shaeffer
  • Patent number: 8947962
    Abstract: A memory controller is disclosed. The memory controller is configured to be connected to one or more memory devices via an address and control (RQ) bus. Each of the memory devices have on-die termination (ODT) circuitry connected to a subset of signal lines of the RQ bus, and the memory controller is operable to selectively disable the ODT circuitry in at least one memory device of the one or more memory devices.
    Type: Grant
    Filed: November 22, 2013
    Date of Patent: February 3, 2015
    Assignee: Rambus Inc.
    Inventors: Ian Shaeffer, Kyung Suk Oh
  • Publication number: 20150023118
    Abstract: In a reconfigurable data strobe-based memory system, data strobes may be re-tasked in different modes of operation. For example, in one mode of operation a differential data strobe may be used as a timing reference for a given set of data signals. In a second mode of operation, one of the components of the differential data strobe may be used as a timing reference for a first portion of the set of data signals and the other component used as a timing reference for a second portion of the set of data signals. Different data mask-related schemes also may be invoked for different modes of operation. For example, in a first mode of operation a memory controller may generate a data mask signal to prevent a portion of a set of data from being written to a memory array. Then, in a second mode of operation the memory controller may invoke a coded value replacement scheme or a data strobe transition inhibition scheme to prevent a portion of a set of data from being written to a memory array.
    Type: Application
    Filed: October 8, 2014
    Publication date: January 22, 2015
    Inventors: Ian Shaeffer, Frederick Ware, Craig E. Hampel