Patents by Inventor Ian St. John

Ian St. John has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and system for entry and verification of parasitic design constraints for analog integrated circuits
    Patent number: 8209650
    Abstract: A method of designing an analog integrated circuit (IC), a parasitic constraint analyzer and a method of determining a layout of an analog IC complies with parasitic constraints. In one embodiment, the method of designing an analog IC includes: (1) creating a schematic of an analog integrated circuit based on a set of specifications, (2) attaching parasitic constraints to the schematic, (3) creating a layout of the analog integrated circuit based on the schematic including the parasitic constraints, (4) extracting parasitic values from parasitic elements of the layout and (5) comparing the extracted parasitic values with the parasitic constraints to verify compliance therewith.
    Type: Grant
    Filed: April 16, 2008
    Date of Patent: June 26, 2012
    Assignee: Texas Instruments Incorporated
    Inventors: Ian St. John, Mohamed Kamal Mahmoud, Baher S. Haroun