Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes multiple processing engines and a power control unit. The power control unit is to receive a mapping of multiple virtual partitions to sets of the processing engines, and in response to a receipt of the mapping of multiple of virtual partitions: access a power limit table for the processor, and generate multiple virtual partition power limit tables based on the power limit table for the processor, where each virtual partition power limit table is associated with a different virtual partition. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

Abstract: A simultaneous multi-threading (SMT) processor core capable of thread-based biasing with respect to execution resources. The SMT processor includes priority controller circuitry to determine a thread priority value for each of a plurality of threads to be executed by the SMT processor core and to generate a priority vector comprising the thread priority value of each of the plurality of threads. The SMT processor further includes thread selector circuitry to make execution cycle assignments of a pipeline by assigning to each of the plurality of threads a portion of the pipeline's execution cycles based on each thread's priority value in the priority vector. The thread selector circuitry is further to select, from the plurality of threads, tasks to be processed by the pipeline based on the execution cycle assignments.

Abstract: In one embodiment, a processor includes at least one core to execute instructions, one or more thermal sensors associated with the at least one core, and a power controller coupled to the at least one core. The power controller has a control logic to receive temperature information regarding the processor and dynamically determine a maximum allowable average power limit based at least in part on the temperature information. The control logic may further maintain a static maximum base operating frequency of the processor regardless of a value of the temperature information. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.

Abstract: In an embodiment, a processor includes a plurality of cores each to independently execute instructions, and a power control unit coupled to the plurality of cores to control power consumption of the processor, where the power control unit includes a control logic to reduce a maximum operating frequency of the processor if a first number of forced performance state transitions occurs in a first time period or a second number of forced performance state transitions occurs in a second time period. Other embodiments are described and claimed.