Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to curvilinear mask models and methods of manufacture. The method includes: calibrating, by a computing device, machine learning models for silicon photonics applications; retargeting, by the computing device, designs in a layout for the silicon photonics applications by applying the machine learning models to the designs; and repairing, by the computing device, unmatching shapes in the retargeted designs to generate final curvilinear mask shapes for the silicon photonics application.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to curvilinear mask models and methods of manufacture. The method includes: calibrating, by a computing device, machine learning models for silicon photonics applications; retargeting, by the computing device, designs in a layout for the silicon photonics applications by applying the machine learning models to the designs; and repairing, by the computing device, unmatching shapes in the retargeted designs to generate final curvilinear mask shapes for the silicon photonics application.

Abstract: A method of and article for determining photomask inspection capabilities. The article comprises a photomask having a first array of a plurality of test pattern shapes that include ordered variations of a first shape variable, from a largest to a smallest dimension, and a second array of a plurality of test pattern shapes, that include the ordered variations of the first shape variable and further include ordered variations of a second shape variable, from a largest to a smallest dimension. The method includes inspecting the first array of test pattern shapes of the photomask in order of the variations of the first shape variable. If at least two consecutive first test pattern shapes in the first array fail an inspection criteria, the failed consecutive first test pattern shapes are marked as failed.

Abstract: An integrated circuit (IC) design method for use as a design and/or manufacturing tool for designing and/or manufacturing integrated circuitry (110). The method utilizes one or more library element (150A-F) to provide a flexible modeling template. Each library element includes one or more module ports (160A-F) each for accepting any one of a plurality of device modules (170). The device modules are logical representations of corresponding respective portions of the integrated circuitry. For any given module port, the corresponding device modules may be interchanged essentially without additional integrated circuitry design changes.