Patents by Inventor Ian Swarbrick
Ian Swarbrick has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10503657Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM). The NVDIMM may be installed in a Dual In-Line Memory Module (DIMM) docket. The NVDIMM may include a non-volatile memory. A device driver may intercept a request for a memory address destined for a host memory controller, replace the memory address with a pre-mapped memory address or an alias of the pre-mapped memory address, and send the pre-mapped memory address to the host memory controller, so that the host memory controller generates a target memory address to NVDIMM.Type: GrantFiled: April 13, 2018Date of Patent: December 10, 2019Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Craig Hanson, Ian Swarbrick, Michael Bekerman, Chihjen Chang
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Patent number: 10121013Abstract: Example embodiments for descrambling and scrambling a memory channel include executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data. The training mode inputs all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device. The scrambled training data are equal to the XOR vectors corresponding to those memory locations. The scrambled training data is received over the memory channel by the memory device and stored as the XOR vectors for each corresponding memory location. During a functional mode, the scrambled data is received over the memory channel for a specified memory location and the XOR vector stored for the specified memory location is used to descramble the scrambled data prior to writing to the specified memory location.Type: GrantFiled: March 8, 2016Date of Patent: November 6, 2018Assignee: Samsung Electronics Co., Ltd.Inventors: Chihjen Chang, Michael Bekerman, Ian Swarbrick, Craig Hanson
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Publication number: 20180239711Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM). The NVDIMM may be installed in a Dual In-Line Memory Module (DIMM) docket. The NVDIMM may include a non-volatile memory. A device driver may intercept a request for a memory address destined for a host memory controller, replace the memory address with a pre-mapped memory address or an alias of the pre-mapped memory address, and send the pre-mapped memory address to the host memory controller, so that the host memory controller generates a target memory address to NVDIMM.Type: ApplicationFiled: April 13, 2018Publication date: August 23, 2018Inventors: Craig HANSON, Ian SWARBRICK, Michael BEKERMAN, Chihjen CHANG
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Patent number: 10031674Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM) (105). The NVDIMM (105) may be installed in a Dual In-Line Memory Module (DIMM) docket (125). The NVDIMM (105) may include a non-volatile memory (130). A device driver (160) may intercept a request for a memory address (605) destined for a host memory controller (115), replace the memory address (605) with a pre-mapped memory address (610) or an alias (705, 710) of the pre-mapped memory address (610), and send the pre-mapped memory address (610) to the host memory controller (115), so that the host memory controller (115) generates a target memory address (615) to NVDIMM (105).Type: GrantFiled: March 3, 2016Date of Patent: July 24, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Craig Hanson, Ian Swarbrick, Michael Bekerman, Chihjen Chang
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Patent number: 10025747Abstract: A protocol that enables communication between a host and an Input/Output (I/O) channel storage device, such as a Dynamic Random Access Memory (DRAM) channel Dual In-Line Memory Module (DIMM) form-factor Solid State Drive (SSD), without the need to know or reverse engineer the encoding applied by the host. The control/status data are written to the storage device by sending a protocol training sequence of known values and storing the associated command/status data in the storage device in the same encoding format as that received from the host. These stored values are used at run time to execute encoded commands received from the host and to report status data to the host in the host-recognizable manner. A memory bank-based buffered configuration stores user data also in the as-received condition to preserve the host-specific encoding. This facilitates exchange of user data between the host memory controller and the storage device over the DRAM channel.Type: GrantFiled: December 11, 2015Date of Patent: July 17, 2018Assignee: SAMSUNG ELECTRONICS CO., LTD.Inventors: Ian Swarbrick, Michael Bekerman, Craig Hanson, Chihjen Chang
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Publication number: 20170102873Abstract: A Non-Volatile Dual In-Line Memory Module is disclosed (NVDIMM) (105). The NVDIMM (105) may be installed in a Dual In-Line Memory Module (DIMM) docket (125). The NVDIMM (105) may include a non-volatile memory (130). A device driver (160) may intercept a request for a memory address (605) destined for a host memory controller (115), replace the memory address (605) with a pre-mapped memory address (610) or an alias (705, 710) of the pre-mapped memory address (610), and send the pre-mapped memory address (610) to the host memory controller (115), so that the host memory controller (115) generates a target memory address (615) to NVDIMM (105).Type: ApplicationFiled: March 3, 2016Publication date: April 13, 2017Inventors: Craig HANSON, Ian SWARBRICK, Michael BEKERMAN, Chihjen CHANG
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Publication number: 20160363986Abstract: A system and a method select a datapath through a meshed Input/Output (IO) fabric. A plurality of port controllers is coupled to interconnection logic. Each port controller is coupled to a corresponding communication link and outputs a detection signal if the corresponding communication link transitions from a first lower-power state to a second higher power state. The interconnection logic, responsive to the detection signal, is configured to output a first signal to one or more selected port controllers to transition the corresponding communication link coupled to the selected port controller from the first power state to the second power state based on a frequency of use of a datapath between the communication link corresponding to the port controller outputting the detection signal and the communication link corresponding to each of the one or more selected port controllers.Type: ApplicationFiled: June 9, 2015Publication date: December 15, 2016Inventors: Ian SWARBRICK, Michael BEKERMAN, Rohit NATARAJAN
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Publication number: 20160328156Abstract: A protocol that enables communication between a host and an Input/Output (I/O) channel storage device, such as a Dynamic Random Access Memory (DRAM) channel Dual In-Line Memory Module (DIMM) form-factor Solid State Drive (SSD), without the need to know or reverse engineer the encoding applied by the host. The control/status data are written to the storage device by sending a protocol training sequence of known values and storing the associated command/status data in the storage device in the same encoding format as that received from the host. These stored values are used at run time to execute encoded commands received from the host and to report status data to the host in the host-recognizable manner. A memory bank-based buffered configuration stores user data also in the as-received condition to preserve the host-specific encoding. This facilitates exchange of user data between the host memory controller and the storage device over the DRAM channel.Type: ApplicationFiled: December 11, 2015Publication date: November 10, 2016Inventors: Ian SWARBRICK, Michael BEKERMAN, Craig HANSON, Chihjen CHANG
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Publication number: 20160328567Abstract: Example embodiments for descrambling and scrambling a memory channel comprise: executing a training mode for the memory device to discover XOR vectors used by the host system to scramble data by: inputting all zero training data to a scrambling algorithm for all memory locations of the memory device to generate scrambled training data that is transmitted over the memory channel to the memory device, such that the scrambled training data are equal to the XOR vectors corresponding to those memory locations; receiving the scrambled training data over memory channel by the memory device and storing the scrambled training data as the XOR vectors for each of the corresponding memory locations; and during a functional mode of the memory device, receiving the scrambled data over the memory channel for a specified memory location, and using the XOR vector stored for the specified memory location to descramble the scrambled data prior to writing to the specified memory location.Type: ApplicationFiled: March 8, 2016Publication date: November 10, 2016Inventors: Chihjen Chang, Michael Bekerman, Ian Swarbrick, Craig Hanson
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Patent number: 9489304Abstract: A system on a chip includes a network, an interface and a bridge module. The network includes one or more devices. The network is configured to operate in a first domain. Communication in the first domain is based on a first set of read and write ordering rules. An interface is connected between the network and a second chip. Communication between the interface and the second chip is in a second domain. Communication in the second domain is based on a second set of read and write ordering rules. The second set of read and write ordering rules are different than the first set of read and write ordering rules. The bridge module is configured to map communication transactions between the first domain and the second domain.Type: GrantFiled: November 14, 2012Date of Patent: November 8, 2016Assignee: Marvell International Ltd.Inventors: Ian Swarbrick, Xiaogang Zhu, Yan Fan
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Patent number: 9264368Abstract: Devices and systems are described for transmitting data packets over a chip-to-chip communications link. For example, a device includes a hardware replay buffer to store a data packet. The data packet includes an overhead portion and a payload portion. Additionally, the transmitter device includes circuitry configured to record a memory location within the hardware replay buffer corresponding to an interruption in transmission to a receiver device of the payload portion of the data packet through a physical serial communications link. The memory location references an intermediate location of the payload portion of the data packet.Type: GrantFiled: January 28, 2013Date of Patent: February 16, 2016Assignee: Marvell World Trade Ltd.Inventors: Ian Swarbrick, Joseph Jun Cao
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Patent number: 9264030Abstract: In one embodiment, a method includes determining, for an integrated circuit chip, a delay measurement corresponding to a first number of stages in a delay line. A power supply voltage measurement is also determined. The method determines a second number of stages correlated to the power supply voltage measurement. The second number of stages correspond to a desired timing delay. It is determined if a power supply voltage should be adjusted using a comparison based on the first number of stages and the second number of stages. A control signal is output for adjusting the power supply voltage when it is determined the power supply voltage should be adjusted.Type: GrantFiled: April 1, 2014Date of Patent: February 16, 2016Assignee: MARVELL INTERNATIONAL LTD.Inventors: Jun Zhu, Joseph Jun Cao, Ian Swarbrick
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Patent number: 8949474Abstract: A system on a chip (SOC) includes a master module, a first swapping module, and a switch module. The master module is configured to generate a transaction request, the transaction request including an address field including an address, the address corresponding to a first slave module associated with the transaction request, and a plurality of interface select bits corresponding to a desired one of a plurality of ports of the first slave module. The first swapping module is configured to swap, in the transaction request, the plurality of interface select bits with selected bits of the address in the address field. The switch module is configured to route the transaction request to the desired one of the plurality of ports based on the address.Type: GrantFiled: November 16, 2012Date of Patent: February 3, 2015Assignee: Marvell International Ltd.Inventors: Ian Swarbrick, Joseph Jun Cao, Jun Zhu
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Patent number: 8826047Abstract: A first power management module includes a power management interface to communicate with a power management bus and manages power states of a first device communicating with a system bus. The power management interface includes a first interface to communicate a first control signal to transition the first device from a first power state to a second power state, a second interface to communicate a second control signal to turn on or off a power supply to the first device, and a third interface to communicate a third control signal to turn on or off a clock of the first device. A second power management module manages power consumption of the first device, independently of a second device communicating with the system bus, based on the power states of the first device using one or more of the first control signal, the second control signal, and the third control signal.Type: GrantFiled: May 16, 2013Date of Patent: September 2, 2014Assignee: Marvell International Ltd.Inventors: Jun Zhu, Ian Swarbrick, Joseph Jun Cao, Sheng Lu, Pantas Sutardja
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Patent number: 8717089Abstract: In one embodiment, a method includes determining, for an integrated circuit chip, a delay measurement corresponding to a first number of stages in a delay line. A power supply voltage measurement is also determined. The method determines a second number of stages correlated to the power supply voltage measurement. The second number of stages correspond to a desired timing delay. It is determined if a power supply voltage should be adjusted using a comparison based on the first number of stages and the second number of stages. A control signal is output for adjusting the power supply voltage when it is determined the power supply voltage should be adjusted.Type: GrantFiled: July 24, 2013Date of Patent: May 6, 2014Assignee: Marvell International Ltd.Inventors: Jun Zhu, Joseph Jun Cao, Ian Swarbrick
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Patent number: 8519781Abstract: In one embodiment, a method includes determining, for an integrated circuit chip, a delay measurement corresponding to a first number of stages in a delay line. A power supply voltage measurement is also determined. The method determines a second number of stages correlated to the power supply voltage measurement. The second number of stages correspond to a desired timing delay. It is determined if a power supply voltage should be adjusted using a comparison based on the first number of stages and the second number of stages. A control signal is output for adjusting the power supply voltage when it is determined the power supply voltage should be adjusted.Type: GrantFiled: January 18, 2013Date of Patent: August 27, 2013Assignee: Marvell International Ltd.Inventors: Jun Zhu, Joseph Jun Cao, Ian Swarbrick
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Patent number: 8448001Abstract: A system includes a first device, a second device, and a main power management module. The first device is configured to communicate with a system bus. The second device is configured to communicate with the system bus. The second device includes a device power management module configured to manage power states of the second device. The main power management module is configured to manage power consumption of the second device independently of the first device by selectively supplying power and clock signals to the second device based on the power states of the second device. The main power management module and the device power management module each comprise a power handshake interface. The main power management module communicates with the device power management module via a power management bus using the power handshake interface.Type: GrantFiled: March 2, 2010Date of Patent: May 21, 2013Assignee: Marvell International Ltd.Inventors: Jun Zhu, Ian Swarbrick, Joseph Jun Cao, Sheng Lu, Pantas Sutardja
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Patent number: 8378738Abstract: In one embodiment, a method includes determining, for an integrated circuit chip, a delay measurement corresponding to a first number of stages in a delay line. A power supply voltage measurement is also determined. The method determines a second number of stages correlated to the power supply voltage measurement. The second number of stages correspond to a desired timing delay. It is determined if a power supply voltage should be adjusted using a comparison based on the first number of stages and the second number of stages. A control signal is output for adjusting the power supply voltage when it is determined the power supply voltage should be adjusted.Type: GrantFiled: October 7, 2010Date of Patent: February 19, 2013Assignee: Marvell International Ltd.Inventors: Jun Zhu, Joseph Jun Cao, Ian Swarbrick
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Patent number: 7290162Abstract: A clock distribution system for an integrated circuit comprising a plurality of regions (1, 2, 3) connected by a communications bus (12). Each region comprises a functional block (10a, 10b, 10c) and at least one bus node (14a, 14b, 14c) for connecting a respective functional block to the communications bus (12). A distributed clock signal (16) is allowed to skew between regions, but synchronised within respective regions. A predetermined clock insertion delay (20a, 20b, 20c, 22a, 22b, 22c) is inserted in each functional block and bus node.Type: GrantFiled: February 14, 2002Date of Patent: October 30, 2007Assignee: Clearspeed Solutions LimitedInventors: Ian Swarbrick, David Williams
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Publication number: 20070083831Abstract: Methods and apparatuses are described for an Intellectual Property (IP) Generator for estimating timing, area, and power characteristics of an electronic system design. The IP Generator receives a user-supplied file having data describing a configuration of an IP design having multiple levels of hierarchy. The IP Generator also receives user-supplied technology parameters and data-flow information. The IP generator correlates estimated timing, area, and power characteristics for each IP sub component based on the user supplied technology parameters, data-flow information and configuration parameters. The IP generator reports the timing, area, and power estimates to a user via a graphic user interface prior to a transformation of a Register Transfer Level (RTL) design into the gate-level circuit design.Type: ApplicationFiled: April 4, 2006Publication date: April 12, 2007Inventors: Stephen Hamilton, Ian Swarbrick, Scott Evans, Wolf-Dietrich Weber, Jay Tomlinson