Abstract: A method for tracking memory changes includes defining a change-track area of memory including at least one memory address range for which changes will be tracked. The method also includes allocating a protected log region of memory for storing a change-track log and selecting an operational mode for change tracking from among a plurality of modes, the selected operational mode having criteria for tracking memory changes. The method includes detecting memory transactions using a memory logging module and generating a transaction record for each memory transaction that occurs in the change-track are of memory and which meets the criteria. The transaction records can be stored in the change-track log.

Abstract: A data processing system comprises a plurality of processors, where each processor is coupled to a respective dedicated memory. The data processing system also comprises a voter module that is disposed between the plurality of processors and one or more peripheral devices such as a network interface, output device, input device, or the like. Each processor provides an I/O transaction to the voter module and the voter module determines whether a majority (or predominate) transaction is present among the I/O transactions received from each of the processors. If a majority transaction is present, the voter module releases the majority transaction to the peripheral. However, if no majority transaction is determined, the system outputs a no majority transaction signal (or raises an exception). Also, a processor error signal (or exception) is output for any processor providing an I/O transaction not corresponding to the majority transaction.

Abstract: An architecture for a reconfigurable network that can be implemented on a semiconductor chip is disclosed, which includes a hierarchical organization of network components and functions that are readily programmable and highly flexible. Essentially, a reconfigurable network on a chip is disclosed, which includes aspects of reconfigurable computing, system on a chip, and network on a chip designs.

Abstract: A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing element. The reconfigurable computer further includes a multi-port communication device comprising a first port at which at least a portion of the raw payload data is written to the multi-port communication device and a second port at which at least a portion raw payload data written to the multi-port communication device is read by the reconfigurable processing element. The reconfigurable computer further includes a controller coupled to the reconfigurable processing element. The controller applies the configuration to the reconfigurable processing element and wherein the controller performs at least one single event upset mitigation operation.

Abstract: An architecture for a reconfigurable network that can be implemented on a semiconductor chip is disclosed, which includes a hierarchical organization of network components and functions that are readily programmable and highly flexible. Essentially, a reconfigurable network on a chip is disclosed, which includes aspects of reconfigurable computing, system on a chip, and network on a chip designs.

Abstract: A reconfigurable computer includes a reconfigurable processing element configured to process raw payload data in accordance with a configuration that is applied to the reconfigurable processing element. The reconfigurable computer further includes a multi-port communication device comprising a first port at which at least a portion of the raw payload data is written to the multi-port communication device and a second port at which at least a portion raw payload data written to the multi-port communication device is read by the reconfigurable processing element. The reconfigurable computer further includes a controller coupled to the reconfigurable processing element. The controller applies the configuration to the reconfigurable processing element and wherein the controller performs at least one single event upset mitigation operation.